pmdomain: imx8mp-blk-ctrl: Keep the NOC_HDCP clock enabled

Keep the NOC_HDCP clock always enabled to fix the potential hang
caused by the NoC ADB400 port power down handshake.

Fixes: 77b0ddb42add ("soc: imx: add i.MX8MP HDMI blk ctrl HDCP/HRV_MWR")
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/pmdomain/imx/imx8mp-blk-ctrl.c b/drivers/pmdomain/imx/imx8mp-blk-ctrl.c
index 8fc79f9723f07e34fd3f5162f2c9c549dcdaeb5b..3f5b9499d30a0c8fb8ad8ba3b638d7de1fc55ab6 100644 (file)
--- a/drivers/pmdomain/imx/imx8mp-blk-ctrl.c
+++ b/drivers/pmdomain/imx/imx8mp-blk-ctrl.c
@@ -352,9 +352,6 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
                regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
                regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
                break;
-       case IMX8MP_HDMIBLK_PD_HDCP:
-               regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
-               break;
        case IMX8MP_HDMIBLK_PD_HRV:
                regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
                regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
@@ -408,9 +405,6 @@ static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
                regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
                regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
                break;
-       case IMX8MP_HDMIBLK_PD_HDCP:
-               regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
-               break;
        case IMX8MP_HDMIBLK_PD_HRV:
                regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
                regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
@@ -439,7 +433,7 @@ static int imx8mp_hdmi_power_notifier(struct notifier_block *nb,
        regmap_write(bc->regmap, HDMI_RTX_CLK_CTL0, 0x0);
        regmap_write(bc->regmap, HDMI_RTX_CLK_CTL1, 0x0);
        regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
-                       BIT(0) | BIT(1) | BIT(10));
+                       BIT(0) | BIT(1) | BIT(10) | BIT(11));
        regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(0));
 
        /*