--- /dev/null
+From e89d120c4b720e232cc6a94f0fcbd59c15d41489 Mon Sep 17 00:00:00 2001
+From: Ionela Voinescu <ionela.voinescu@arm.com>
+Date: Fri, 19 Aug 2022 11:30:50 +0100
+Subject: arm64: errata: add detection for AMEVCNTR01 incrementing incorrectly
+
+From: Ionela Voinescu <ionela.voinescu@arm.com>
+
+commit e89d120c4b720e232cc6a94f0fcbd59c15d41489 upstream.
+
+The AMU counter AMEVCNTR01 (constant counter) should increment at the same
+rate as the system counter. On affected Cortex-A510 cores, AMEVCNTR01
+increments incorrectly giving a significantly higher output value. This
+results in inaccurate task scheduler utilization tracking and incorrect
+feedback on CPU frequency.
+
+Work around this problem by returning 0 when reading the affected counter
+in key locations that results in disabling all users of this counter from
+using it either for frequency invariance or as FFH reference counter. This
+effect is the same to firmware disabling affected counters.
+
+Details on how the two features are affected by this erratum:
+
+ - AMU counters will not be used for frequency invariance for affected
+ CPUs and CPUs in the same cpufreq policy. AMUs can still be used for
+ frequency invariance for unaffected CPUs in the system. Although
+ unlikely, if no alternative method can be found to support frequency
+ invariance for affected CPUs (cpufreq based or solution based on
+ platform counters) frequency invariance will be disabled. Please check
+ the chapter on frequency invariance at
+ Documentation/scheduler/sched-capacity.rst for details of its effect.
+
+ - Given that FFH can be used to fetch either the core or constant counter
+ values, restrictions are lifted regarding any of these counters
+ returning a valid (!0) value. Therefore FFH is considered supported
+ if there is a least one CPU that support AMUs, independent of any
+ counters being disabled or affected by this erratum. Clarifying
+ comments are now added to the cpc_ffh_supported(), cpu_read_constcnt()
+ and cpu_read_corecnt() functions.
+
+The above is achieved through adding a new erratum: ARM64_ERRATUM_2457168.
+
+Signed-off-by: Ionela Voinescu <ionela.voinescu@arm.com>
+Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
+Cc: Catalin Marinas <catalin.marinas@arm.com>
+Cc: Will Deacon <will@kernel.org>
+Cc: James Morse <james.morse@arm.com>
+Link: https://lore.kernel.org/r/20220819103050.24211-1-ionela.voinescu@arm.com
+Signed-off-by: Will Deacon <will@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ Documentation/arm64/silicon-errata.rst | 2 ++
+ arch/arm64/Kconfig | 18 ++++++++++++++++++
+ arch/arm64/include/asm/cpucaps.h | 3 ++-
+ arch/arm64/kernel/cpu_errata.c | 9 +++++++++
+ arch/arm64/kernel/cpufeature.c | 5 ++++-
+ 5 files changed, 35 insertions(+), 2 deletions(-)
+
+--- a/Documentation/arm64/silicon-errata.rst
++++ b/Documentation/arm64/silicon-errata.rst
+@@ -92,6 +92,8 @@ stable kernels.
+ +----------------+-----------------+-----------------+-----------------------------+
+ | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
+ +----------------+-----------------+-----------------+-----------------------------+
++| ARM | Cortex-A510 | #2457168 | ARM64_ERRATUM_2457168 |
+++----------------+-----------------+-----------------+-----------------------------+
+ | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
+ +----------------+-----------------+-----------------+-----------------------------+
+ | ARM | Neoverse-N1 | #1349291 | N/A |
+--- a/arch/arm64/Kconfig
++++ b/arch/arm64/Kconfig
+@@ -657,6 +657,24 @@ config ARM64_ERRATUM_1508412
+
+ If unsure, say Y.
+
++config ARM64_ERRATUM_2457168
++ bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
++ depends on ARM64_AMU_EXTN
++ default y
++ help
++ This option adds the workaround for ARM Cortex-A510 erratum 2457168.
++
++ The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
++ as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
++ incorrectly giving a significantly higher output value.
++
++ Work around this problem by keeping the reference values of affected counters
++ to 0 thus signaling an error case. This effect is the same to firmware disabling
++ affected counters, in which case 0 will be returned when reading the disabled
++ counters.
++
++ If unsure, say Y.
++
+ config CAVIUM_ERRATUM_22375
+ bool "Cavium erratum 22375, 24313"
+ default y
+--- a/arch/arm64/include/asm/cpucaps.h
++++ b/arch/arm64/include/asm/cpucaps.h
+@@ -67,7 +67,8 @@
+ #define ARM64_MTE 57
+ #define ARM64_WORKAROUND_1508412 58
+ #define ARM64_SPECTRE_BHB 59
++#define ARM64_WORKAROUND_2457168 60
+
+-#define ARM64_NCAPS 60
++#define ARM64_NCAPS 61
+
+ #endif /* __ASM_CPUCAPS_H */
+--- a/arch/arm64/kernel/cpu_errata.c
++++ b/arch/arm64/kernel/cpu_errata.c
+@@ -546,6 +546,15 @@ const struct arm64_cpu_capabilities arm6
+ 1, 0),
+ },
+ #endif
++#ifdef CONFIG_ARM64_ERRATUM_2457168
++ {
++ .desc = "ARM erratum 2457168",
++ .capability = ARM64_WORKAROUND_2457168,
++ .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
++ /* Cortex-A510 r0p0-r1p1 */
++ CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1)
++ },
++#endif
+ {
+ }
+ };
+--- a/arch/arm64/kernel/cpufeature.c
++++ b/arch/arm64/kernel/cpufeature.c
+@@ -1559,7 +1559,10 @@ static void cpu_amu_enable(struct arm64_
+ pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
+ smp_processor_id());
+ cpumask_set_cpu(smp_processor_id(), &amu_cpus);
+- init_cpu_freq_invariance_counters();
++
++ /* 0 reference values signal broken/disabled counters */
++ if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168))
++ init_cpu_freq_invariance_counters();
+ }
+ }
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
