Revert "drop queue-4.9/arm-8843-1-use-unified-assembler-in-headers.patch"

This reverts commit 6eb6862d45d130f2c3681e686235b4b55eb5e67f.

diff --git a/queue-4.9/arm-8843-1-use-unified-assembler-in-headers.patch b/queue-4.9/arm-8843-1-use-unified-assembler-in-headers.patch
new file mode 100644 (file)
index 0000000..0a94546
--- /dev/null
+++ b/queue-4.9/arm-8843-1-use-unified-assembler-in-headers.patch
@@ -0,0 +1,148 @@
+From eea60ff4d4e95ee775c7455b3abaa9c8546c95fc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 18 Feb 2019 00:56:58 +0100
+Subject: ARM: 8843/1: use unified assembler in headers
+
+From: Stefan Agner <stefan@agner.ch>
+
+[ Upstream commit c001899a5d6c2d7a0f3b75b2307ddef137fb46a6 ]
+
+Use unified assembler syntax (UAL) in headers. Divided syntax is
+considered deprecated. This will also allow to build the kernel
+using LLVM's integrated assembler.
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Acked-by: Nicolas Pitre <nico@linaro.org>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/include/asm/assembler.h | 12 ++++++------
+ arch/arm/include/asm/vfpmacros.h |  8 ++++----
+ arch/arm/lib/bitops.h            |  8 ++++----
+ 3 files changed, 14 insertions(+), 14 deletions(-)
+
+diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
+index 7d727506096f..c9ed0b0e0737 100644
+--- a/arch/arm/include/asm/assembler.h
++++ b/arch/arm/include/asm/assembler.h
+@@ -372,9 +372,9 @@ THUMB(     orr     \reg , \reg , #PSR_T_BIT        )
+       .macro  usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
+ 9999:
+       .if     \inc == 1
+-      \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
++      \instr\()b\t\cond\().w \reg, [\ptr, #\off]
+       .elseif \inc == 4
+-      \instr\cond\()\t\().w \reg, [\ptr, #\off]
++      \instr\t\cond\().w \reg, [\ptr, #\off]
+       .else
+       .error  "Unsupported inc macro argument"
+       .endif
+@@ -413,9 +413,9 @@ THUMB(     orr     \reg , \reg , #PSR_T_BIT        )
+       .rept   \rept
+ 9999:
+       .if     \inc == 1
+-      \instr\cond\()b\()\t \reg, [\ptr], #\inc
++      \instr\()b\t\cond \reg, [\ptr], #\inc
+       .elseif \inc == 4
+-      \instr\cond\()\t \reg, [\ptr], #\inc
++      \instr\t\cond \reg, [\ptr], #\inc
+       .else
+       .error  "Unsupported inc macro argument"
+       .endif
+@@ -456,7 +456,7 @@ THUMB(     orr     \reg , \reg , #PSR_T_BIT        )
+       .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
+ #ifndef CONFIG_CPU_USE_DOMAINS
+       adds    \tmp, \addr, #\size - 1
+-      sbcccs  \tmp, \tmp, \limit
++      sbcscc  \tmp, \tmp, \limit
+       bcs     \bad
+ #ifdef CONFIG_CPU_SPECTRE
+       movcs   \addr, #0
+@@ -470,7 +470,7 @@ THUMB(     orr     \reg , \reg , #PSR_T_BIT        )
+       sub     \tmp, \limit, #1
+       subs    \tmp, \tmp, \addr       @ tmp = limit - 1 - addr
+       addhs   \tmp, \tmp, #1          @ if (tmp >= 0) {
+-      subhss  \tmp, \tmp, \size       @ tmp = limit - (addr + size) }
++      subshs  \tmp, \tmp, \size       @ tmp = limit - (addr + size) }
+       movlo   \addr, #0               @ if (tmp < 0) addr = NULL
+       csdb
+ #endif
+diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
+index 301c1db3e99b..66748c04aed2 100644
+--- a/arch/arm/include/asm/vfpmacros.h
++++ b/arch/arm/include/asm/vfpmacros.h
+@@ -28,13 +28,13 @@
+       ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
+       ldr     \tmp, [\tmp, #0]
+       tst     \tmp, #HWCAP_VFPD32
+-      ldcnel  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
++      ldclne  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
+       addeq   \base, \base, #32*4                 @ step over unused register space
+ #else
+       VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
+       and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
+       cmp     \tmp, #2                            @ 32 x 64bit registers?
+-      ldceql  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
++      ldcleq  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
+       addne   \base, \base, #32*4                 @ step over unused register space
+ #endif
+ #endif
+@@ -52,13 +52,13 @@
+       ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
+       ldr     \tmp, [\tmp, #0]
+       tst     \tmp, #HWCAP_VFPD32
+-      stcnel  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
++      stclne  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
+       addeq   \base, \base, #32*4                 @ step over unused register space
+ #else
+       VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
+       and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
+       cmp     \tmp, #2                            @ 32 x 64bit registers?
+-      stceql  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
++      stcleq  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
+       addne   \base, \base, #32*4                 @ step over unused register space
+ #endif
+ #endif
+diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
+index 7d807cfd8ef5..d9c32b822eda 100644
+--- a/arch/arm/lib/bitops.h
++++ b/arch/arm/lib/bitops.h
+@@ -6,7 +6,7 @@
+ ENTRY(        \name           )
+ UNWIND(       .fnstart        )
+       ands    ip, r1, #3
+-      strneb  r1, [ip]                @ assert word-aligned
++      strbne  r1, [ip]                @ assert word-aligned
+       mov     r2, #1
+       and     r3, r0, #31             @ Get bit offset
+       mov     r0, r0, lsr #5
+@@ -31,7 +31,7 @@ ENDPROC(\name                )
+ ENTRY(        \name           )
+ UNWIND(       .fnstart        )
+       ands    ip, r1, #3
+-      strneb  r1, [ip]                @ assert word-aligned
++      strbne  r1, [ip]                @ assert word-aligned
+       mov     r2, #1
+       and     r3, r0, #31             @ Get bit offset
+       mov     r0, r0, lsr #5
+@@ -61,7 +61,7 @@ ENDPROC(\name                )
+ ENTRY(        \name           )
+ UNWIND(       .fnstart        )
+       ands    ip, r1, #3
+-      strneb  r1, [ip]                @ assert word-aligned
++      strbne  r1, [ip]                @ assert word-aligned
+       and     r2, r0, #31
+       mov     r0, r0, lsr #5
+       mov     r3, #1
+@@ -88,7 +88,7 @@ ENDPROC(\name                )
+ ENTRY(        \name           )
+ UNWIND(       .fnstart        )
+       ands    ip, r1, #3
+-      strneb  r1, [ip]                @ assert word-aligned
++      strbne  r1, [ip]                @ assert word-aligned
+       and     r3, r0, #31
+       mov     r0, r0, lsr #5
+       save_and_disable_irqs ip
+-- 
+2.25.1
+

diff --git a/queue-4.9/series b/queue-4.9/series
index f7100e257cb348b9ff643a81723e6fc1ab974082..14efe01a514c573b7ca818766f8c5ded23d81cef 100644 (file)
--- a/queue-4.9/series
+++ b/queue-4.9/series
@@ -23,6 +23,7 @@ input-evdev-call-input_flush_device-on-release-not-f.patch
 input-xpad-add-custom-init-packet-for-xbox-one-s-con.patch
 input-i8042-add-thinkpad-s230u-to-i8042-reset-list.patch
 input-synaptics-rmi4-fix-error-return-code-in-rmi_dr.patch
+arm-8843-1-use-unified-assembler-in-headers.patch
 arm-uaccess-consolidate-uaccess-asm-to-asm-uaccess-a.patch
 arm-uaccess-integrate-uaccess_save-and-uaccess_resto.patch
 arm-uaccess-fix-dacr-mismatch-with-nested-exceptions.patch