drm/i915/xe3p_lpd: Extend FBC support to UINT16 formats

Starting Xe3p_LPD, FBC is supported on UINT16 formats as well. Also
UINT16 being a 64bpp format, will use cpp of 8 for cfb stride and thus
size calculations.

v2: simplify getting the cpp per format (Ville)
    simplify the pixel format is valid for xe3p_lp (Vinod)

Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
BSpec: 68881, 68904, 69560
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20251027134001.325064-2-vinod.govindapillai@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 6e5cf522ef5b6cb7814b41581313c91402dbb63f..a06db84525fc9e072b0e86430628f8f62bf85007 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -141,15 +141,18 @@ static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane
        return stride;
 }
 
-static unsigned int intel_fbc_cfb_cpp(void)
+static unsigned int intel_fbc_cfb_cpp(const struct intel_plane_state *plane_state)
 {
-       return 4; /* FBC always 4 bytes per pixel */
+       const struct drm_framebuffer *fb = plane_state->hw.fb;
+       unsigned int cpp = fb->format->cpp[0];
+
+       return max(cpp, 4);
 }
 
 /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */
 static unsigned int intel_fbc_plane_cfb_stride(const struct intel_plane_state *plane_state)
 {
-       unsigned int cpp = intel_fbc_cfb_cpp();
+       unsigned int cpp = intel_fbc_cfb_cpp(plane_state);
 
        return intel_fbc_plane_stride(plane_state) * cpp;
 }
@@ -203,7 +206,7 @@ static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_s
        struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
        unsigned int stride = intel_fbc_plane_cfb_stride(plane_state);
        unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16;
-       unsigned int cpp = intel_fbc_cfb_cpp();
+       unsigned int cpp = intel_fbc_cfb_cpp(plane_state);
 
        return _intel_fbc_cfb_stride(display, cpp, width, stride);
 }
@@ -1081,11 +1084,31 @@ static bool lnl_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_
        }
 }
 
+static bool xe3p_lpd_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
+{
+       const struct drm_framebuffer *fb = plane_state->hw.fb;
+
+       if (lnl_fbc_pixel_format_is_valid(plane_state))
+               return true;
+
+       switch (fb->format->format) {
+       case DRM_FORMAT_XRGB16161616:
+       case DRM_FORMAT_XBGR16161616:
+       case DRM_FORMAT_ARGB16161616:
+       case DRM_FORMAT_ABGR16161616:
+               return true;
+       default:
+               return false;
+       }
+}
+
 static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
 {
        struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
 
-       if (DISPLAY_VER(display) >= 20)
+       if (DISPLAY_VER(display) >= 35)
+               return xe3p_lpd_fbc_pixel_format_is_valid(plane_state);
+       else if (DISPLAY_VER(display) >= 20)
                return lnl_fbc_pixel_format_is_valid(plane_state);
        else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
                return g4x_fbc_pixel_format_is_valid(plane_state);