spi: cadence-quadspi: Flush posted register writes before DAC access

commit 1ad55767e77a853c98752ed1e33b68049a243bd7 upstream.

cqspi_read_setup() and cqspi_write_setup() program the address width as
the last step in the setup. This is likely to be immediately followed by
a DAC region read/write. On TI K3 SoCs the DAC region is on a different
endpoint from the register region. This means that the order of the two
operations is not guaranteed, and they might be reordered at the
interconnect level. It is possible that the DAC read/write goes through
before the address width update goes through. In this situation if the
previous command used a different address width the OSPI command is sent
with the wrong number of address bytes, resulting in an invalid command
and undefined behavior.

Read back the size register to make sure the write gets flushed before
accessing the DAC region.

Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller")
CC: stable@vger.kernel.org
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
Signed-off-by: Pratyush Yadav <pratyush@kernel.org>
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Message-ID: <20250905185958.3575037-3-s-k6@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index deb83cc34be176bc4e7054eca27868c64c5fa3ee..91fdc9132b962ff66ebc40dd6656f1cb7ad4f18b 100644 (file)
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -666,6 +666,7 @@ static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
        reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
        reg |= (op->addr.nbytes - 1);
        writel(reg, reg_base + CQSPI_REG_SIZE);
+       readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */
        return 0;
 }
 
@@ -810,6 +811,7 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
        reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
        reg |= (op->addr.nbytes - 1);
        writel(reg, reg_base + CQSPI_REG_SIZE);
+       readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */
        return 0;
 }