drm/amdgpu/vce1: Enable VCE1 on Tahiti, Pitcairn, Cape Verde GPUs

Add the VCE1 IP block to the SI GPUs that have it.
Advertise the encoder capabilities corresponding to VCE1,
so the userspace applications can detect and use it.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Co-developed-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index e0f139de79915a7477cab97040a5bc841e3963df..9d769222784c4bb08c5a930fdbc1a68c104c0ca7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -45,6 +45,7 @@
 #include "dce_v6_0.h"
 #include "si.h"
 #include "uvd_v3_1.h"
+#include "vce_v1_0.h"
 
 #include "uvd/uvd_4_0_d.h"
 
@@ -921,8 +922,6 @@ static const u32 hainan_mgcg_cgcg_init[] =
        0x3630, 0xfffffff0, 0x00000100,
 };
 
-/* XXX: update when we support VCE */
-#if 0
 /* tahiti, pitcairn, verde */
 static const struct amdgpu_video_codec_info tahiti_video_codecs_encode_array[] =
 {
@@ -940,13 +939,7 @@ static const struct amdgpu_video_codecs tahiti_video_codecs_encode =
        .codec_count = ARRAY_SIZE(tahiti_video_codecs_encode_array),
        .codec_array = tahiti_video_codecs_encode_array,
 };
-#else
-static const struct amdgpu_video_codecs tahiti_video_codecs_encode =
-{
-       .codec_count = 0,
-       .codec_array = NULL,
-};
-#endif
+
 /* oland and hainan don't support encode */
 static const struct amdgpu_video_codecs hainan_video_codecs_encode =
 {
@@ -2717,7 +2710,7 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
                else
                        amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block);
                amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block);
-               /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
+               amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block);
                break;
        case CHIP_OLAND:
                amdgpu_device_ip_block_add(adev, &si_common_ip_block);
@@ -2735,7 +2728,6 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
                else
                        amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block);
                amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block);
-               /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
                break;
        case CHIP_HAINAN:
                amdgpu_device_ip_block_add(adev, &si_common_ip_block);