#define ZYNQ_GEM_BASEADDR1 0xE000C000
#define ZYNQ_SDHCI_BASEADDR0 0xE0100000
#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
+#define ZYNQ_I2C_BASEADDR0 0xE0004000
+#define ZYNQ_I2C_BASEADDR1 0xE0005000
/* Reflect slcr offsets */
struct slcr_regs {
#include <asm/io.h>
#include <i2c.h>
#include <asm/errno.h>
+#include <asm/arch/hardware.h>
/* i2c register set */
struct zynq_i2c_registers {
#define ZYNQ_I2C_INTERRUPT_RXUNF 0x00000080
#define ZYNQ_I2C_INTERRUPT_ARBLOST 0x00000200
-#if defined(CONFIG_ZYNQ_I2C_CTLR_0)
-#define ZYNQ_I2C_BASE 0xE0004000
-#if defined(CONFIG_ZYNQ_I2C_CTLR_1)
-#warning Only CONFIG_ZYNQ_I2C_CTLR_0 will be accessible
-#endif
-#elif defined(CONFIG_ZYNQ_I2C_CTLR_1)
-#define ZYNQ_I2C_BASE 0xE0005000
-#else
-#error You must select CONFIG_ZYNQ_I2C_CTLR_0 or CONFIG_ZYNQ_I2C_CTLR_1
-#endif
-
#define ZYNQ_I2C_FIFO_DEPTH 16
#define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */
+#if defined(CONFIG_ZYNQ_I2C0)
+# define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR0
+#else
+# define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR1
+#endif
+
static struct zynq_i2c_registers *zynq_i2c =
(struct zynq_i2c_registers *)ZYNQ_I2C_BASE;
# define CONFIG_DOS_PARTITION
#endif
+#define CONFIG_ZYNQ_I2C0
+
+/* I2C */
+#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
+# define CONFIG_CMD_I2C
+# define CONFIG_ZYNQ_I2C
+# define CONFIG_HARD_I2C
+# define CONFIG_SYS_I2C_SPEED 100000
+# define CONFIG_SYS_I2C_SLAVE 1
+#endif
+
#if defined(CONFIG_ZYNQ_DCC)
# define CONFIG_ARM_DCC
# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
/* I2C */
#ifdef CONFIG_ZYNQ_I2C
# define CONFIG_CMD_I2C
-# define CONFIG_ZYNQ_I2C_CTLR_0
+# define CONFIG_ZYNQ_I2C0
# define CONFIG_HARD_I2C 1
# define CONFIG_SYS_I2C_SPEED 100000
# define CONFIG_SYS_I2C_SLAVE 1