riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE

Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive
SYS_CACHE_SHIFT_6 to enable it.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
index 4d9581165bf05cc797a507fcf493005db54d6868..c1d3e6ada23f600abf4125f24847f1c40e00d44e 100644 (file)
--- a/arch/riscv/cpu/jh7110/Kconfig
+++ b/arch/riscv/cpu/jh7110/Kconfig
@@ -13,6 +13,7 @@ config STARFIVE_JH7110
        select SUPPORT_SPL
        select SPL_RAM if SPL
        select SPL_STARFIVE_DDR
+       select SYS_CACHE_SHIFT_6
        select PINCTRL_STARFIVE_JH7110
        imply MMC
        imply MMC_BROKEN_CD