sse.md (*ssse3_palignr<mode>_perm): New.

gcc/
	* config/i386/sse.md (*ssse3_palignr<mode>_perm): New.
	* config/i386/predicates.md (palignr_operand): New.
	Indicates if permutation is suitable for palignr instruction.

From-SVN: r211264

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 98d56a5ceedeaefe4ad9495c91be753967534878..6167424f7762ab9c736a7f4a754f9a617d0b935b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2014-06-05  Evgeny Stupachenko  <evstupac@gmail.com>
+
+       * config/i386/sse.md (*ssse3_palignr<mode>_perm): New.
+       * config/i386/predicates.md (palignr_operand): New.
+       Indicates if permutation is suitable for palignr instruction.
+
 2014-06-05  Yuri Rumyantsev  <ysrumyan@gmail.com>
 
        PR tree-optimization/61319

diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index efc3a090d08a9d5f087d7c0d72140234d92ddefb..300c1688d2638dea97d3e8017d0e3eb80027873b 100644 (file)
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -1425,6 +1425,22 @@
   return true;
 })
 
+;; Return true if OP is a parallel for a palignr permute.
+(define_predicate "palignr_operand"
+  (and (match_code "parallel")
+       (match_code "const_int" "a"))
+{
+  int elt = INTVAL (XVECEXP (op, 0, 0));
+  int i, nelt = XVECLEN (op, 0);
+
+  /* Check that an order in the permutation is suitable for palignr.
+     For example, {5 6 7 0 1 2 3 4} is "palignr 5, xmm, xmm".  */
+  for (i = 1; i < nelt; ++i)
+    if (INTVAL (XVECEXP (op, 0, i)) != ((elt + i) % nelt))
+      return false;
+  return true;
+})
+
 ;; Return true if OP is a proper third operand to vpblendw256.
 (define_predicate "avx2_pblendw_operand"
   (match_code "const_int")

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index c91626bac196a3493e04cd6cd06cd9b97e8fee50..d9073535d0eabcdfd3f63708e7e8c2c87caaea9f 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -14551,6 +14551,35 @@
    (set_attr "prefix" "vex")
    (set_attr "mode" "<sseinsnmode>")])
 
+(define_insn "*ssse3_palignr<mode>_perm"
+  [(set (match_operand:V_128 0 "register_operand" "=x,x")
+      (vec_select:V_128
+       (match_operand:V_128 1 "register_operand" "0,x")
+       (match_parallel 2 "palignr_operand"
+         [(match_operand 3 "const_int_operand" "n, n")])))]
+  "TARGET_SSSE3"
+{
+  enum machine_mode imode = GET_MODE_INNER (GET_MODE (operands[0]));
+  operands[2] = GEN_INT (INTVAL (operands[3]) * GET_MODE_SIZE (imode));
+
+  switch (which_alternative)
+    {
+    case 0:
+      return "palignr\t{%2, %1, %0|%0, %1, %2}";
+    case 1:
+      return "vpalignr\t{%2, %1, %1, %0|%0, %1, %1, %2}";
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseishft")
+   (set_attr "atom_unit" "sishuf")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
+   (set_attr "prefix" "orig,vex")])
+
 (define_expand "avx_vinsertf128<mode>"
   [(match_operand:V_256 0 "register_operand")
    (match_operand:V_256 1 "register_operand")