drm/xe: Rename send_tlb_inval_ppgtt to send_tlb_inval_asid_ppgtt

Context-based TLB invalidations have their own set of GuC TLB
invalidation operations. Rename the current PPGTT invalidation function,
which operates on ASIDs, to a more descriptive name that reflects its
purpose.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Tested-by: Stuart Summers <stuart.summers@intel.com>
Link: https://patch.msgid.link/20260116221731.868657-8-matthew.brost@intel.com

diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
index 43f6dbcb2bc24d22fbcec5d3af796ea9c7d97569..a6a1c371a28edefbfd5cc05ea8292b4461d98c67 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
@@ -150,9 +150,9 @@ static u64 normalize_invalidation_range(struct xe_gt *gt, u64 *start, u64 *end)
  */
 #define MAX_RANGE_TLB_INVALIDATION_LENGTH (rounddown_pow_of_two(ULONG_MAX))
 
-static int send_tlb_inval_ppgtt(struct xe_tlb_inval *tlb_inval, u32 seqno,
-                               u64 start, u64 end, u32 asid,
-                               struct drm_suballoc *prl_sa)
+static int send_tlb_inval_asid_ppgtt(struct xe_tlb_inval *tlb_inval, u32 seqno,
+                                    u64 start, u64 end, u32 asid,
+                                    struct drm_suballoc *prl_sa)
 {
 #define MAX_TLB_INVALIDATION_LEN       7
        struct xe_guc *guc = tlb_inval->private;
@@ -219,7 +219,7 @@ static long tlb_inval_timeout_delay(struct xe_tlb_inval *tlb_inval)
 static const struct xe_tlb_inval_ops guc_tlb_inval_ops = {
        .all = send_tlb_inval_all,
        .ggtt = send_tlb_inval_ggtt,
-       .ppgtt = send_tlb_inval_ppgtt,
+       .ppgtt = send_tlb_inval_asid_ppgtt,
        .initialized = tlb_inval_initialized,
        .flush = tlb_inval_flush,
        .timeout_delay = tlb_inval_timeout_delay,