[AArch64] Disable vec_perm patterns for aarch64_be.

From-SVN: r206851

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a57bffec83cf1fbc8a05d3ab0a3183cce1d4b305..7815479a7116123014e53d8e56252b9ead91db95 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2014-01-20  Alex Velenko  <Alex.Velenko@arm.com>
+
+       * config/aarch64/aarch64-simd.md (vec_perm<mode>): Add BE check.
+
 2014-01-20  Jakub Jelinek  <jakub@redhat.com>
 
        PR middle-end/59860

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index bc47a291de4b9b24d829e4dbf060fff7a321558f..43a9c5b27d78a47cf965636a03232005a4c8e7c3 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3840,7 +3840,7 @@
    (match_operand:VB 1 "register_operand")
    (match_operand:VB 2 "register_operand")
    (match_operand:VB 3 "register_operand")]
-  "TARGET_SIMD"
+  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
 {
   aarch64_expand_vec_perm (operands[0], operands[1],
                           operands[2], operands[3]);

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8f66ea95642f3a33dff48653ea5548040fa0e3e0..073e20ca66e9f70792888b4f980e7e96bf150f13 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2014-01-20  Alex Velenko  <Alex.Velenko@arm.com>
+
+       * lib/target-supports.exp
+       (check_effective_target_vect_perm): Exclude aarch64_be.
+       (check_effective_target_vect_perm_byte): Likewise.
+       (check_effective_target_vect_perm_short): Likewise.
+
 2013-01-20  Alex Velenko  <Alex.Velenko@arm.com>
 
        * gcc.target/aarch64/vneg_f.c (STORE_INST): New macro.

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index ebb28aeb39f86415aa410beed22da4dd4acd530a..eea0c2e238c93718ace1c87e26660d62dc21b342 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3440,7 +3440,8 @@ proc check_effective_target_vect_perm { } {
     } else {
         set et_vect_perm_saved 0
         if { [is-effective-target arm_neon_ok]
-            || [istarget aarch64*-*-*]
+            || ([istarget aarch64*-*-*]
+                && [is-effective-target aarch64_little_endian])
             || [istarget powerpc*-*-*]
              || [istarget spu-*-*]
             || [istarget i?86-*-*]
@@ -3468,7 +3469,8 @@ proc check_effective_target_vect_perm_byte { } {
         set et_vect_perm_byte_saved 0
         if { ([is-effective-target arm_neon_ok]
              && [is-effective-target arm_little_endian])
-            || [istarget aarch64*-*-*]
+            || ([istarget aarch64*-*-*]
+                && [is-effective-target aarch64_little_endian])
             || [istarget powerpc*-*-*]
              || [istarget spu-*-*] } {
             set et_vect_perm_byte_saved 1
@@ -3492,7 +3494,8 @@ proc check_effective_target_vect_perm_short { } {
         set et_vect_perm_short_saved 0
         if { ([is-effective-target arm_neon_ok]
              && [is-effective-target arm_little_endian])
-            || [istarget aarch64*-*-*]
+            || ([istarget aarch64*-*-*]
+                && [is-effective-target aarch64_little_endian])
             || [istarget powerpc*-*-*]
              || [istarget spu-*-*] } {
             set et_vect_perm_short_saved 1