ASoC: wm8974: Correct PLL rate rounding

[ Upstream commit 9b17d3724df55ecc2bc67978822585f2b023be48 ]

Using a single value of 22500000 for both 48000Hz and 44100Hz audio
will sometimes result in returning wrong dividers due to rounding.
Update the code to use the actual value for both.

Fixes: 51b2bb3f2568 ("ASoC: wm8974: configure pll and mclk divider automatically")
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://patch.msgid.link/20250821082639.1301453-4-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/sound/soc/codecs/wm8974.c b/sound/soc/codecs/wm8974.c
index 600e93d61a90fa35c76c201f4a992e04bdac26bb..bfc72c2bf90b852e7a0523d69eff3f42ec9fef61 100644 (file)
--- a/sound/soc/codecs/wm8974.c
+++ b/sound/soc/codecs/wm8974.c
@@ -419,10 +419,14 @@ static int wm8974_update_clocks(struct snd_soc_dai *dai)
        fs256 = 256 * priv->fs;
 
        f = wm8974_get_mclkdiv(priv->mclk, fs256, &mclkdiv);
-
        if (f != priv->mclk) {
                /* The PLL performs best around 90MHz */
-               fpll = wm8974_get_mclkdiv(22500000, fs256, &mclkdiv);
+               if (fs256 % 8000)
+                       f = 22579200;
+               else
+                       f = 24576000;
+
+               fpll = wm8974_get_mclkdiv(f, fs256, &mclkdiv);
        }
 
        wm8974_set_dai_pll(dai, 0, 0, priv->mclk, fpll);