drm/amd/display: Avoid turning off the PHY when OTG is running for DVI

[Why]
The OTG's virtual pixel clock source for DVI comes from the PHY.

If the signal type is DVI then the OTG can become stuck on pre DCN401
ASIC when DPMS off occurs because the OTG remains running but the
PHY transmitter is disabled.

[How]
There exists logic to keep track of the OTG running refcount on the
link to determine if the link needs to go to PLL_EN instead of TX_EN
but the logic only checks for HDMI TMDS on older ASIC.

DVI is still a TMDS signal type so the constraint should also apply.

Replace the checks for dc_is_hdmi_tmds_signal with dc_is_tmds_signal to
cover both HDMI and DVI for the symclk refcount workaround.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 8a17cc036399ad89751ec7bbf96aee4606a996dd..d2025779d036f8e139cb734153f162ca6bd48fd7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -1568,7 +1568,7 @@ static enum dc_status dce110_enable_stream_timing(
                        return DC_ERROR_UNEXPECTED;
                }
 
-               if (dc_is_hdmi_tmds_signal(stream->signal)) {
+               if (dc_is_tmds_signal(stream->signal)) {
                        stream->link->phy_state.symclk_ref_cnts.otg = 1;
                        if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
                                stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
@@ -2418,7 +2418,7 @@ static void dce110_reset_hw_ctx_wrap(
                                BREAK_TO_DEBUGGER();
                        }
                        pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
-                       if (dc_is_hdmi_tmds_signal(pipe_ctx_old->stream->signal))
+                       if (dc_is_tmds_signal(pipe_ctx_old->stream->signal))
                                pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
                        pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
                                        pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 307e8f8060e6da8ede09d075fa2e4074f5655ebe..a673ab0803a8f45d373ccc21df3da0613887c0cc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -893,7 +893,7 @@ enum dc_status dcn20_enable_stream_timing(
                dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
        }
 
-       if (dc_is_hdmi_tmds_signal(stream->signal)) {
+       if (dc_is_tmds_signal(stream->signal)) {
                stream->link->phy_state.symclk_ref_cnts.otg = 1;
                if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
                        stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
@@ -2856,7 +2856,7 @@ void dcn20_reset_back_end_for_pipe(
                 * the case where the same symclk is shared across multiple otg
                 * instances
                 */
-               if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+               if (dc_is_tmds_signal(pipe_ctx->stream->signal))
                        link->phy_state.symclk_ref_cnts.otg = 0;
                if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
                        link_hwss->disable_link_output(link,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index 94f63fd54e3eb9282b5b3bc07920d432fc801a79..1fba44aecdd321845a1e193fe2b1a93aede93879 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -548,7 +548,7 @@ static void dcn31_reset_back_end_for_pipe(
         * the case where the same symclk is shared across multiple otg
         * instances
         */
-       if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+       if (dc_is_tmds_signal(pipe_ctx->stream->signal))
                link->phy_state.symclk_ref_cnts.otg = 0;
 
        if (pipe_ctx->top_pipe == NULL) {

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index a72284c3fa1c91e792da14fccebdb8e7b8b5fbac..ca611b3c22d3a550e6a3fb85c451cd92e6fee713 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1938,7 +1938,7 @@ void dcn401_reset_back_end_for_pipe(
                 * the case where the same symclk is shared across multiple otg
                 * instances
                 */
-               if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+               if (dc_is_tmds_signal(pipe_ctx->stream->signal))
                        link->phy_state.symclk_ref_cnts.otg = 0;
                if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
                        link_hwss->disable_link_output(link,