re PR target/11089 (ICE: instantiate_virtual_regs_lossage while using sse built-ins)

        PR target/11089
        * config/i386/i386.md (sse_movaps): Use an expander to force
        one operand to be a register.
        (sse_movups): Likewise.

From-SVN: r67883

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cec44af1546ed85a8ba5101b6d765f1ec853a9ec..5396c79ce1ff4fcd85aea9cb889f411a64bc4ecc 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2003-06-12  Richard Henderson  <rth@redhat.com>
+
+       PR target/11089
+       * config/i386/i386.md (sse_movaps): Use an expander to force
+       one operand to be a register.
+       (sse_movups): Likewise.
+
 2003-06-13  Doug Evans  <dje@sebabeach.org>
 
        Remove some build warnings.

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 850e9a1dfdc1a81e6417be1dcfe5f0caa357c8cc..faf0e5a5b98b0ea9c38861c8c6f2c9b6e1c4d488 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -19530,7 +19530,22 @@
 
 ;; These two patterns are useful for specifying exactly whether to use
 ;; movaps or movups
-(define_insn "sse_movaps"
+(define_expand "sse_movaps"
+  [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
+       (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
+                    UNSPEC_MOVA))]
+  "TARGET_SSE"
+{
+  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+    {
+      rtx tmp = gen_reg_rtx (V4SFmode);
+      emit_insn (gen_sse_movaps (tmp, operands[1]));
+      emit_move_insn (operands[0], tmp);
+      DONE;
+    }
+})
+
+(define_insn "*sse_movaps_1"
   [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
        (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
                     UNSPEC_MOVA))]
@@ -19540,7 +19555,22 @@
   [(set_attr "type" "ssemov,ssemov")
    (set_attr "mode" "V4SF")])
 
-(define_insn "sse_movups"
+(define_expand "sse_movups"
+  [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
+       (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
+                    UNSPEC_MOVU))]
+  "TARGET_SSE"
+{
+  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+    {
+      rtx tmp = gen_reg_rtx (V4SFmode);
+      emit_insn (gen_sse_movups (tmp, operands[1]));
+      emit_move_insn (operands[0], tmp);
+      DONE;
+    }
+})
+
+(define_insn "*sse_movups_1"
   [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
        (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
                     UNSPEC_MOVU))]
@@ -19550,7 +19580,6 @@
   [(set_attr "type" "ssecvt,ssecvt")
    (set_attr "mode" "V4SF")])
 
-
 ;; SSE Strange Moves.
 
 (define_insn "sse_movmskps"

diff --git a/gcc/testsuite/gcc.dg/i386-sse-4.c b/gcc/testsuite/gcc.dg/i386-sse-4.c
new file mode 100644 (file)
index 0000000..c94e7f8
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/i386-sse-4.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-O0 -msse" } */
+
+typedef void __vr __attribute__ ((__mode__ (__V4SF__)));
+
+struct vector
+{
+  union
+  {
+    __vr v;
+    float f[4];
+  };
+};
+
+void
+doit ()
+{
+  float f[4];
+  struct vector v;
+
+  f[0] = 0;
+  f[1] = 1;
+  f[2] = 2;
+  f[3] = 3;
+
+  v.v = __builtin_ia32_loadups (f);
+}