drop tegra patch that broke the build

diff --git a/queue-5.10/series b/queue-5.10/series
index 04590539172d7db54cd4d02aac8bd73333880178..433cd5fb3a685c8901f1368c8714ba3790a81198 100644 (file)
--- a/queue-5.10/series
+++ b/queue-5.10/series
@@ -47,7 +47,6 @@ selftests-bpf-fix-bpf_prog_detach2-usage-in-test_lir.patch
 cpufreq-longhaul-handle-null-policy-in-longhaul_exit.patch
 arc-fix-__fls-const-foldability-via-__builtin_clzl.patch
 irqchip-gic-v2m-handle-multiple-msi-base-irq-alignme.patch
-soc-tegra-fuse-add-tegra114-nvmem-cells-and-fuse-loo.patch
 mmc-sdhci-msm-enable-tuning-for-sdr50-mode-for-sd-ca.patch
 acpica-dispatcher-use-acpi_ds_clear_operands-in-acpi.patch
 tee-allow-a-driver-to-allocate-a-tee_device-without-.patch

diff --git a/queue-5.10/soc-tegra-fuse-add-tegra114-nvmem-cells-and-fuse-loo.patch b/queue-5.10/soc-tegra-fuse-add-tegra114-nvmem-cells-and-fuse-loo.patch
deleted file mode 100644 (file)
index 4660184..0000000
--- a/queue-5.10/soc-tegra-fuse-add-tegra114-nvmem-cells-and-fuse-loo.patch
+++ /dev/null
@@ -1,163 +0,0 @@
-From 82accbe0ec50bce22a53065beef6d3fde7552bfb Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 28 Aug 2025 08:50:59 +0300
-Subject: soc/tegra: fuse: Add Tegra114 nvmem cells and fuse lookups
-
-From: Svyatoslav Ryhel <clamor95@gmail.com>
-
-[ Upstream commit b9c01adedf38c69abb725a60a05305ef70dbce03 ]
-
-Add missing Tegra114 nvmem cells and fuse lookups which were added for
-Tegra124+ but omitted for Tegra114.
-
-Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
-Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
-Signed-off-by: Thierry Reding <treding@nvidia.com>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/soc/tegra/fuse/fuse-tegra30.c | 122 ++++++++++++++++++++++++++
- 1 file changed, 122 insertions(+)
-
-diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c
-index c1aa7815bd6ec..f7f1a73a52f3a 100644
---- a/drivers/soc/tegra/fuse/fuse-tegra30.c
-+++ b/drivers/soc/tegra/fuse/fuse-tegra30.c
-@@ -117,6 +117,124 @@ const struct tegra_fuse_soc tegra30_fuse_soc = {
- #endif
- 
- #ifdef CONFIG_ARCH_TEGRA_114_SOC
-+static const struct nvmem_cell_info tegra114_fuse_cells[] = {
-+      {
-+              .name = "tsensor-cpu1",
-+              .offset = 0x084,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-cpu2",
-+              .offset = 0x088,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-common",
-+              .offset = 0x08c,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-cpu0",
-+              .offset = 0x098,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "xusb-pad-calibration",
-+              .offset = 0x0f0,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-cpu3",
-+              .offset = 0x12c,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-gpu",
-+              .offset = 0x154,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-mem0",
-+              .offset = 0x158,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-mem1",
-+              .offset = 0x15c,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-pllx",
-+              .offset = 0x160,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      },
-+};
-+
-+static const struct nvmem_cell_lookup tegra114_fuse_lookups[] = {
-+      {
-+              .nvmem_name = "fuse",
-+              .cell_name = "xusb-pad-calibration",
-+              .dev_id = "7009f000.padctl",
-+              .con_id = "calibration",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-common",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "common",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-cpu0",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "cpu0",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-cpu1",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "cpu1",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-cpu2",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "cpu2",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-cpu3",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "cpu3",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-mem0",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "mem0",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-mem1",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "mem1",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-gpu",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "gpu",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-pllx",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "pllx",
-+      },
-+};
-+
- static const struct tegra_fuse_info tegra114_fuse_info = {
-       .read = tegra30_fuse_read,
-       .size = 0x2a0,
-@@ -127,6 +245,10 @@ const struct tegra_fuse_soc tegra114_fuse_soc = {
-       .init = tegra30_fuse_init,
-       .speedo_init = tegra114_init_speedo_data,
-       .info = &tegra114_fuse_info,
-+      .lookups = tegra114_fuse_lookups,
-+      .num_lookups = ARRAY_SIZE(tegra114_fuse_lookups),
-+      .cells = tegra114_fuse_cells,
-+      .num_cells = ARRAY_SIZE(tegra114_fuse_cells),
-       .soc_attr_group = &tegra_soc_attr_group,
- };
- #endif
--- 
-2.51.0
-

diff --git a/queue-5.15/series b/queue-5.15/series
index 035666598f1a19a44dd67991c50d428dcf035ba9..393bfa8691340d3d956723cb223a10d536a9d6f3 100644 (file)
--- a/queue-5.15/series
+++ b/queue-5.15/series
@@ -67,7 +67,6 @@ acpi-prm-skip-handlers-with-null-handler_address-or-.patch
 acpi-scan-add-intel-cvs-acpi-hids-to-acpi_ignore_dep.patch
 hwmon-sbtsi_temp-amd-cpu-extended-temperature-range-.patch
 power-supply-sbs-charger-support-multiple-devices.patch
-soc-tegra-fuse-add-tegra114-nvmem-cells-and-fuse-loo.patch
 mmc-sdhci-msm-enable-tuning-for-sdr50-mode-for-sd-ca.patch
 acpica-dispatcher-use-acpi_ds_clear_operands-in-acpi.patch
 tee-allow-a-driver-to-allocate-a-tee_device-without-.patch

diff --git a/queue-5.15/soc-tegra-fuse-add-tegra114-nvmem-cells-and-fuse-loo.patch b/queue-5.15/soc-tegra-fuse-add-tegra114-nvmem-cells-and-fuse-loo.patch
deleted file mode 100644 (file)
index a0cfeae..0000000
--- a/queue-5.15/soc-tegra-fuse-add-tegra114-nvmem-cells-and-fuse-loo.patch
+++ /dev/null
@@ -1,163 +0,0 @@
-From 8d4471231acb0d9c5c6eb78daf571ddc46c18428 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 28 Aug 2025 08:50:59 +0300
-Subject: soc/tegra: fuse: Add Tegra114 nvmem cells and fuse lookups
-
-From: Svyatoslav Ryhel <clamor95@gmail.com>
-
-[ Upstream commit b9c01adedf38c69abb725a60a05305ef70dbce03 ]
-
-Add missing Tegra114 nvmem cells and fuse lookups which were added for
-Tegra124+ but omitted for Tegra114.
-
-Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
-Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
-Signed-off-by: Thierry Reding <treding@nvidia.com>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/soc/tegra/fuse/fuse-tegra30.c | 122 ++++++++++++++++++++++++++
- 1 file changed, 122 insertions(+)
-
-diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c
-index b071d433d74f8..bfc8d39ae9efd 100644
---- a/drivers/soc/tegra/fuse/fuse-tegra30.c
-+++ b/drivers/soc/tegra/fuse/fuse-tegra30.c
-@@ -117,6 +117,124 @@ const struct tegra_fuse_soc tegra30_fuse_soc = {
- #endif
- 
- #ifdef CONFIG_ARCH_TEGRA_114_SOC
-+static const struct nvmem_cell_info tegra114_fuse_cells[] = {
-+      {
-+              .name = "tsensor-cpu1",
-+              .offset = 0x084,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-cpu2",
-+              .offset = 0x088,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-common",
-+              .offset = 0x08c,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-cpu0",
-+              .offset = 0x098,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "xusb-pad-calibration",
-+              .offset = 0x0f0,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-cpu3",
-+              .offset = 0x12c,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-gpu",
-+              .offset = 0x154,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-mem0",
-+              .offset = 0x158,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-mem1",
-+              .offset = 0x15c,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-pllx",
-+              .offset = 0x160,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      },
-+};
-+
-+static const struct nvmem_cell_lookup tegra114_fuse_lookups[] = {
-+      {
-+              .nvmem_name = "fuse",
-+              .cell_name = "xusb-pad-calibration",
-+              .dev_id = "7009f000.padctl",
-+              .con_id = "calibration",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-common",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "common",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-cpu0",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "cpu0",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-cpu1",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "cpu1",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-cpu2",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "cpu2",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-cpu3",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "cpu3",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-mem0",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "mem0",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-mem1",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "mem1",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-gpu",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "gpu",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-pllx",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "pllx",
-+      },
-+};
-+
- static const struct tegra_fuse_info tegra114_fuse_info = {
-       .read = tegra30_fuse_read,
-       .size = 0x2a0,
-@@ -127,6 +245,10 @@ const struct tegra_fuse_soc tegra114_fuse_soc = {
-       .init = tegra30_fuse_init,
-       .speedo_init = tegra114_init_speedo_data,
-       .info = &tegra114_fuse_info,
-+      .lookups = tegra114_fuse_lookups,
-+      .num_lookups = ARRAY_SIZE(tegra114_fuse_lookups),
-+      .cells = tegra114_fuse_cells,
-+      .num_cells = ARRAY_SIZE(tegra114_fuse_cells),
-       .soc_attr_group = &tegra_soc_attr_group,
-       .clk_suspend_on = false,
- };
--- 
-2.51.0
-

diff --git a/queue-6.1/series b/queue-6.1/series
index cc44882dd07e0f15963f797fddf4c413a8d5bca5..6f882c278fbba80a7a49cffc163ce42090c19929 100644 (file)
--- a/queue-6.1/series
+++ b/queue-6.1/series
@@ -104,7 +104,6 @@ hwmon-sbtsi_temp-amd-cpu-extended-temperature-range-.patch
 power-supply-sbs-charger-support-multiple-devices.patch
 hwmon-sy7636a-add-alias.patch
 irqchip-loongson-pch-lpc-use-legacy-domain-for-pch-l.patch
-soc-tegra-fuse-add-tegra114-nvmem-cells-and-fuse-loo.patch
 mmc-sdhci-msm-enable-tuning-for-sdr50-mode-for-sd-ca.patch
 acpica-dispatcher-use-acpi_ds_clear_operands-in-acpi.patch
 tee-allow-a-driver-to-allocate-a-tee_device-without-.patch

diff --git a/queue-6.1/soc-tegra-fuse-add-tegra114-nvmem-cells-and-fuse-loo.patch b/queue-6.1/soc-tegra-fuse-add-tegra114-nvmem-cells-and-fuse-loo.patch
deleted file mode 100644 (file)
index c80322e..0000000
--- a/queue-6.1/soc-tegra-fuse-add-tegra114-nvmem-cells-and-fuse-loo.patch
+++ /dev/null
@@ -1,163 +0,0 @@
-From a33b90f3941b1bf87a148d8a6cc74f9d178ad053 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 28 Aug 2025 08:50:59 +0300
-Subject: soc/tegra: fuse: Add Tegra114 nvmem cells and fuse lookups
-
-From: Svyatoslav Ryhel <clamor95@gmail.com>
-
-[ Upstream commit b9c01adedf38c69abb725a60a05305ef70dbce03 ]
-
-Add missing Tegra114 nvmem cells and fuse lookups which were added for
-Tegra124+ but omitted for Tegra114.
-
-Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
-Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
-Signed-off-by: Thierry Reding <treding@nvidia.com>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/soc/tegra/fuse/fuse-tegra30.c | 122 ++++++++++++++++++++++++++
- 1 file changed, 122 insertions(+)
-
-diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c
-index f01d8a2547b6d..01f212057ee34 100644
---- a/drivers/soc/tegra/fuse/fuse-tegra30.c
-+++ b/drivers/soc/tegra/fuse/fuse-tegra30.c
-@@ -117,6 +117,124 @@ const struct tegra_fuse_soc tegra30_fuse_soc = {
- #endif
- 
- #ifdef CONFIG_ARCH_TEGRA_114_SOC
-+static const struct nvmem_cell_info tegra114_fuse_cells[] = {
-+      {
-+              .name = "tsensor-cpu1",
-+              .offset = 0x084,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-cpu2",
-+              .offset = 0x088,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-common",
-+              .offset = 0x08c,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-cpu0",
-+              .offset = 0x098,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "xusb-pad-calibration",
-+              .offset = 0x0f0,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-cpu3",
-+              .offset = 0x12c,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-gpu",
-+              .offset = 0x154,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-mem0",
-+              .offset = 0x158,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-mem1",
-+              .offset = 0x15c,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      }, {
-+              .name = "tsensor-pllx",
-+              .offset = 0x160,
-+              .bytes = 4,
-+              .bit_offset = 0,
-+              .nbits = 32,
-+      },
-+};
-+
-+static const struct nvmem_cell_lookup tegra114_fuse_lookups[] = {
-+      {
-+              .nvmem_name = "fuse",
-+              .cell_name = "xusb-pad-calibration",
-+              .dev_id = "7009f000.padctl",
-+              .con_id = "calibration",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-common",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "common",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-cpu0",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "cpu0",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-cpu1",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "cpu1",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-cpu2",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "cpu2",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-cpu3",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "cpu3",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-mem0",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "mem0",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-mem1",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "mem1",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-gpu",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "gpu",
-+      }, {
-+              .nvmem_name = "fuse",
-+              .cell_name = "tsensor-pllx",
-+              .dev_id = "700e2000.thermal-sensor",
-+              .con_id = "pllx",
-+      },
-+};
-+
- static const struct tegra_fuse_info tegra114_fuse_info = {
-       .read = tegra30_fuse_read,
-       .size = 0x2a0,
-@@ -127,6 +245,10 @@ const struct tegra_fuse_soc tegra114_fuse_soc = {
-       .init = tegra30_fuse_init,
-       .speedo_init = tegra114_init_speedo_data,
-       .info = &tegra114_fuse_info,
-+      .lookups = tegra114_fuse_lookups,
-+      .num_lookups = ARRAY_SIZE(tegra114_fuse_lookups),
-+      .cells = tegra114_fuse_cells,
-+      .num_cells = ARRAY_SIZE(tegra114_fuse_cells),
-       .soc_attr_group = &tegra_soc_attr_group,
-       .clk_suspend_on = false,
- };
--- 
-2.51.0
-