]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
zynq: Do not enable icache
authorMichal Simek <michal.simek@xilinx.com>
Tue, 7 May 2013 13:01:20 +0000 (15:01 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 14 May 2013 16:07:33 +0000 (18:07 +0200)
icache is already turned on.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/cpu/armv7/zynq/cpu.c
board/xilinx/zynq/board.c
include/configs/petalogix-arm-auto.h
include/configs/zynq_common.h

index e8f4c19d4908c9d208c0eb6259f53dfef11d4ad7..156cb0099ab914467262ba4aca9c70e1bee39b34 100644 (file)
@@ -55,3 +55,11 @@ void reset_cpu(ulong addr)
        while (1)
                ;
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+        /* Enable D-cache. I-cache is already enabled in start.S */
+        dcache_enable();
+}
+#endif
index 979ddb1392811aeca1a0d790a3a0497f74bf250f..da2abe4c06656d05231f67d3aa2c1d4781b9960d 100644 (file)
@@ -84,8 +84,6 @@ int board_init(void)
        writel(0x00, 0xe000a040);
        writel(0x80, 0xe000a040);
 
-       icache_enable();
-
 #ifdef CONFIG_FPGA
        fpga_init();
        fpga_add(fpga_xilinx, &fpga);
index 13b797aa584411446da00496d2c7adb520c55321..c352701333e636d3e7e92d4bcbf3a68d04ce5d95 100644 (file)
 # endif
 #endif
 
+#define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_SYS_CACHELINE_SIZE      32 /* Assuming bytes? */
 
+/* Keep L2 Cache Disabled */
+#define CONFIG_SYS_L2CACHE_OFF
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+# define CONFIG_SYS_L2_PL310
+# define CONFIG_SYS_PL310_BASE  0xf8f02000
+#endif
+
 #define CONFIG_NR_DRAM_BANKS           1
 
 /*-----------------------------------------------------------------------
index 4e87cbe9620f71affd1b706a919513cc63177e60..fe638c6594c68681c0a2c88c3b5bcb4b27040d20 100644 (file)
 #define CONFIG_BOOTDELAY               3 /* -1 to Disable autoboot */
 #define CONFIG_SYS_LOAD_ADDR           0 /* default? */
 
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+
 /* Keep L2 Cache Disabled */
 #define CONFIG_SYS_L2CACHE_OFF
 #define CONFIG_SYS_CACHELINE_SIZE      32
 
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE  0xf8f02000
+#endif
+
 /* Physical Memory map */
 #define CONFIG_NR_DRAM_BANKS           1
 #define PHYS_SDRAM_1                   0