icache is already turned on.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
while (1)
;
}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
writel(0x00, 0xe000a040);
writel(0x80, 0xe000a040);
- icache_enable();
-
#ifdef CONFIG_FPGA
fpga_init();
fpga_add(fpga_xilinx, &fpga);
# endif
#endif
+#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_CACHELINE_SIZE 32 /* Assuming bytes? */
+/* Keep L2 Cache Disabled */
+#define CONFIG_SYS_L2CACHE_OFF
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+# define CONFIG_SYS_L2_PL310
+# define CONFIG_SYS_PL310_BASE 0xf8f02000
+#endif
+
#define CONFIG_NR_DRAM_BANKS 1
/*-----------------------------------------------------------------------
#define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */
#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+
/* Keep L2 Cache Disabled */
#define CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_CACHELINE_SIZE 32
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE 0xf8f02000
+#endif
+
/* Physical Memory map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0