]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
ntb_hw_amd: Update amd_ntb_get_link_status to support latest generation secondary...
authorBasavaraj Natikar <Basavaraj.Natikar@amd.com>
Thu, 18 Sep 2025 07:34:47 +0000 (13:04 +0530)
committerJon Mason <jdmason@kudzu.us>
Mon, 22 Sep 2025 13:35:20 +0000 (09:35 -0400)
In the NTB secondary topology configuration of the latest generation,
the device behaves like an endpoint. Hence, add endpoint support and
update amd_ntb_get_link_status to accommodate endpoint devices.

Co-developed-by: Sanath S <Sanath.S@amd.com>
Signed-off-by: Sanath S <Sanath.S@amd.com>
Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
drivers/ntb/hw/amd/ntb_hw_amd.c
drivers/ntb/hw/amd/ntb_hw_amd.h

index 63ceed89b62ef9cf65cad0af033b2fffcfc7a3bb..1a163596ddf54ec9824a6e9e844494c5f9505a9d 100644 (file)
@@ -197,13 +197,22 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
 
 static int amd_ntb_get_link_status(struct amd_ntb_dev *ndev)
 {
-       struct pci_dev *pdev = NULL;
+       struct pci_dev *pdev = ndev->ntb.pdev;
        struct pci_dev *pci_swds = NULL;
        struct pci_dev *pci_swus = NULL;
        u32 stat;
        int rc;
 
        if (ndev->ntb.topo == NTB_TOPO_SEC) {
+               if (ndev->dev_data->is_endpoint) {
+                       rc = pcie_capability_read_dword(pdev, PCI_EXP_LNKCTL, &stat);
+                       if (rc)
+                               return rc;
+
+                       ndev->lnk_sta = stat;
+                       return 0;
+               }
+
                /* Locate the pointer to Downstream Switch for this device */
                pci_swds = pci_upstream_bridge(ndev->ntb.pdev);
                if (pci_swds) {
@@ -1311,6 +1320,11 @@ static const struct ntb_dev_data dev_data[] = {
                .mw_count = 2,
                .mw_idx = 2,
        },
+       { /* for device 0x17d7 */
+               .mw_count = 2,
+               .mw_idx = 2,
+               .is_endpoint = true,
+       },
 };
 
 static const struct pci_device_id amd_ntb_pci_tbl[] = {
@@ -1319,6 +1333,8 @@ static const struct pci_device_id amd_ntb_pci_tbl[] = {
        { PCI_VDEVICE(AMD, 0x14c0), (kernel_ulong_t)&dev_data[1] },
        { PCI_VDEVICE(AMD, 0x14c3), (kernel_ulong_t)&dev_data[1] },
        { PCI_VDEVICE(AMD, 0x155a), (kernel_ulong_t)&dev_data[1] },
+       { PCI_VDEVICE(AMD, 0x17d4), (kernel_ulong_t)&dev_data[1] },
+       { PCI_VDEVICE(AMD, 0x17d7), (kernel_ulong_t)&dev_data[2] },
        { PCI_VDEVICE(HYGON, 0x145b), (kernel_ulong_t)&dev_data[0] },
        { 0, }
 };
index 5f337b1572a0841d792804ac877b4a2266d5f1b4..e8c3165fa38be9dc54d6440caf40165a48a280ff 100644 (file)
@@ -168,6 +168,7 @@ enum {
 struct ntb_dev_data {
        const unsigned char mw_count;
        const unsigned int mw_idx;
+       const bool is_endpoint;
 };
 
 struct amd_ntb_dev;