Xilinx: ARM: Update to support PEEP 9 NOR flash changes.

 NOR flash is now at 0xE2000000, not 0xE4000000.

diff --git a/board/xilinx/dfe/board.c b/board/xilinx/dfe/board.c
index 086c8c8bc43b4a6124f69394afac2691569ac54c..2e8ca86953e7fff1060299a455748b7a09f0165a 100644 (file)
--- a/board/xilinx/dfe/board.c
+++ b/board/xilinx/dfe/board.c
@@ -6,7 +6,7 @@
 #include <xparameters.h>
 
 #define PARPORT_CRTL_BASEADDR                   XPSS_CRTL_PARPORT_BASEADDR
-#define NOR_FLASH_BASEADDR                      XPSS_PARPORT1_BASEADDR
+#define NOR_FLASH_BASEADDR                      XPSS_PARPORT0_BASEADDR
 
 #define PARPORT_MC_DIRECT_CMD                   0x010
 #define PARPORT_MC_SET_CYCLES                   0x014
@@ -56,7 +56,7 @@ void init_nor_flash()
 
   /* write operation mode to set_opmode registers */
   u32 set_opmode_reg = (0x1 << 13) | /* set_burst_align, see to 32 beats */
-                       (0x0 << 12) | /* set_bls, set to default I am not sure */
+                       (0x1 << 12) | /* set_bls, set to default */
                        (0x0 << 11) | /* set_adv bit, set to default */
                        (0x0 << 10) | /* set_baa, I guess we don't use baa_n */
                        (0x0 << 7) |  /* set_wr_bl, write brust length, set to 0 */
@@ -68,12 +68,12 @@ void init_nor_flash()
 
   /*
    * Issue a direct_cmd by writing to direct_cmd register
-   * This is needed becuase the UpdatesReg flag in direct_cmd updates the state of SMC
-   * I think....
+   * This is needed becuase the UpdatesReg flag in direct_cmd updates the
+   * state of SMC
    */
-  u32 direct_cmd_reg = (0x1 << 23) | /* chip 1 from interface 0 */
+  u32 direct_cmd_reg = (0x0 << 23) | /* chip 1 from interface 0 */
                        (0x2 << 21) | /* UpdateRegs operation, to update the two reg we wrote earlier*/
-                       (0x0 << 20) | /* Not sure about this one cre, what does it do? */
+                       (0x0 << 20) | /* cre */
                        (0x0);        /* addr, not use in UpdateRegs */
   Out32(PARPORT_CRTL_BASEADDR + PARPORT_MC_DIRECT_CMD, direct_cmd_reg);
 

diff --git a/include/configs/xpele.h b/include/configs/xpele.h
index ce1207899230f284bd1ec71884a2648bde306f91..a6558b0144457b7eaa6e36b4d5ed9a4e4ce34c2e 100644 (file)
--- a/include/configs/xpele.h
+++ b/include/configs/xpele.h
@@ -29,9 +29,9 @@
        "nand_kernel_size=0x400000\0"   \
        "nand_ramdisk_size=0x400000\0"  \
        "norboot=echo Copying Linux from NOR flash to RAM...;                   \
-                           cp 0xE4100000 0x8000 ${kernel_size};                \
+                           cp 0xE2100000 0x8000 ${kernel_size};                \
                            echo Copying ramdisk from NOR flash to RAM...;      \
-                           cp 0xE5000000 0x800000 ${ramdisk_size};             \
+                           cp 0xE3000000 0x800000 ${ramdisk_size};             \
                            go 0x8000\0"                                        \
        "qspiboot=echo Copying Linux from QSPI flash to RAM...;                 \
                            cp 0xFC100000 0x8000 ${kernel_size};                \
@@ -99,7 +99,7 @@
 #ifndef CONFIG_SYS_NO_FLASH
 
 /* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE           0xE4000000 
+#define CONFIG_SYS_FLASH_BASE           0xE2000000 
 #define CONFIG_SYS_FLASH_SIZE           (16*1024*1024)  /* i.e. 16MB */
 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors/blocks on one chip */

diff --git a/xromhdr.pl b/xromhdr.pl
index 9ed3f73eaa87636e587e1fae7f8f7029b8d62553..0a37fc8ff469854c2d2d705b3cd96151169bdd39 100755 (executable)
--- a/xromhdr.pl
+++ b/xromhdr.pl
@@ -66,7 +66,7 @@ $HDR_38 = 0x00000000;
 
 $HDR_3C = 0xDEADBEEF;
 if ($hdr_type eq "nor") {
- $HDR_3C = 0xE40000A8;
+ $HDR_3C = 0xE20000A8;
 } 
 if ($hdr_type eq "qspi") {
  $HDR_3C = 0xFC0000A8;