--- /dev/null
+From c92a54cfa0257e8ffd66b2a17d49e9c0bd4b769f Mon Sep 17 00:00:00 2001
+From: "Lendacky, Thomas" <Thomas.Lendacky@amd.com>
+Date: Mon, 17 Dec 2018 14:39:16 +0000
+Subject: dma-direct: do not include SME mask in the DMA supported check
+
+From: Lendacky, Thomas <Thomas.Lendacky@amd.com>
+
+commit c92a54cfa0257e8ffd66b2a17d49e9c0bd4b769f upstream.
+
+The dma_direct_supported() function intends to check the DMA mask against
+specific values. However, the phys_to_dma() function includes the SME
+encryption mask, which defeats the intended purpose of the check. This
+results in drivers that support less than 48-bit DMA (SME encryption mask
+is bit 47) from being able to set the DMA mask successfully when SME is
+active, which results in the driver failing to initialize.
+
+Change the function used to check the mask from phys_to_dma() to
+__phys_to_dma() so that the SME encryption mask is not part of the check.
+
+Fixes: c1d0af1a1d5d ("kernel/dma/direct: take DMA offset into account in dma_direct_supported")
+Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
+Signed-off-by: Christoph Hellwig <hch@lst.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+
+---
+ kernel/dma/direct.c | 13 +++++++++++--
+ 1 file changed, 11 insertions(+), 2 deletions(-)
+
+--- a/kernel/dma/direct.c
++++ b/kernel/dma/direct.c
+@@ -168,7 +168,12 @@ int dma_direct_map_sg(struct device *dev
+ int dma_direct_supported(struct device *dev, u64 mask)
+ {
+ #ifdef CONFIG_ZONE_DMA
+- if (mask < phys_to_dma(dev, DMA_BIT_MASK(ARCH_ZONE_DMA_BITS)))
++ /*
++ * This check needs to be against the actual bit mask value, so
++ * use __phys_to_dma() here so that the SME encryption mask isn't
++ * part of the check.
++ */
++ if (mask < __phys_to_dma(dev, DMA_BIT_MASK(ARCH_ZONE_DMA_BITS)))
+ return 0;
+ #else
+ /*
+@@ -176,8 +181,12 @@ int dma_direct_supported(struct device *
+ * to be able to satisfy them - either by not supporting more physical
+ * memory, or by providing a ZONE_DMA32. If neither is the case, the
+ * architecture needs to use an IOMMU instead of the direct mapping.
++ *
++ * This check needs to be against the actual bit mask value, so
++ * use __phys_to_dma() here so that the SME encryption mask isn't
++ * part of the check.
+ */
+- if (mask < phys_to_dma(dev, DMA_BIT_MASK(32)))
++ if (mask < __phys_to_dma(dev, DMA_BIT_MASK(32)))
+ return 0;
+ #endif
+ /*
--- /dev/null
+From 4bd46aa0353e022c2401a258e93b107880a66533 Mon Sep 17 00:00:00 2001
+From: Brad Love <brad@nextdimension.cc>
+Date: Wed, 19 Dec 2018 12:07:01 -0500
+Subject: media: cx23885: only reset DMA on problematic CPUs
+
+From: Brad Love <brad@nextdimension.cc>
+
+commit 4bd46aa0353e022c2401a258e93b107880a66533 upstream.
+
+It is reported that commit 95f408bbc4e4 ("media: cx23885: Ryzen DMA
+related RiSC engine stall fixes") caused regresssions with other CPUs.
+
+Ensure that the quirk will be applied only for the CPUs that
+are known to cause problems.
+
+A module option is added for explicit control of the behaviour.
+
+Fixes: 95f408bbc4e4 ("media: cx23885: Ryzen DMA related RiSC engine stall fixes")
+
+Signed-off-by: Brad Love <brad@nextdimension.cc>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/media/pci/cx23885/cx23885-core.c | 55 +++++++++++++++++++++++++++++--
+ drivers/media/pci/cx23885/cx23885.h | 2 +
+ 2 files changed, 55 insertions(+), 2 deletions(-)
+
+--- a/drivers/media/pci/cx23885/cx23885-core.c
++++ b/drivers/media/pci/cx23885/cx23885-core.c
+@@ -23,6 +23,7 @@
+ #include <linux/moduleparam.h>
+ #include <linux/kmod.h>
+ #include <linux/kernel.h>
++#include <linux/pci.h>
+ #include <linux/slab.h>
+ #include <linux/interrupt.h>
+ #include <linux/delay.h>
+@@ -41,6 +42,18 @@ MODULE_AUTHOR("Steven Toth <stoth@linuxt
+ MODULE_LICENSE("GPL");
+ MODULE_VERSION(CX23885_VERSION);
+
++/*
++ * Some platforms have been found to require periodic resetting of the DMA
++ * engine. Ryzen and XEON platforms are known to be affected. The symptom
++ * encountered is "mpeg risc op code error". Only Ryzen platforms employ
++ * this workaround if the option equals 1. The workaround can be explicitly
++ * disabled for all platforms by setting to 0, the workaround can be forced
++ * on for any platform by setting to 2.
++ */
++static unsigned int dma_reset_workaround = 1;
++module_param(dma_reset_workaround, int, 0644);
++MODULE_PARM_DESC(dma_reset_workaround, "periodic RiSC dma engine reset; 0-force disable, 1-driver detect (default), 2-force enable");
++
+ static unsigned int debug;
+ module_param(debug, int, 0644);
+ MODULE_PARM_DESC(debug, "enable debug messages");
+@@ -603,8 +616,13 @@ static void cx23885_risc_disasm(struct c
+
+ static void cx23885_clear_bridge_error(struct cx23885_dev *dev)
+ {
+- uint32_t reg1_val = cx_read(TC_REQ); /* read-only */
+- uint32_t reg2_val = cx_read(TC_REQ_SET);
++ uint32_t reg1_val, reg2_val;
++
++ if (!dev->need_dma_reset)
++ return;
++
++ reg1_val = cx_read(TC_REQ); /* read-only */
++ reg2_val = cx_read(TC_REQ_SET);
+
+ if (reg1_val && reg2_val) {
+ cx_write(TC_REQ, reg1_val);
+@@ -2058,6 +2076,37 @@ void cx23885_gpio_enable(struct cx23885_
+ /* TODO: 23-19 */
+ }
+
++static struct {
++ int vendor, dev;
++} const broken_dev_id[] = {
++ /* According with
++ * https://openbenchmarking.org/system/1703021-RI-AMDZEN08075/Ryzen%207%201800X/lspci,
++ * 0x1451 is PCI ID for the IOMMU found on Ryzen
++ */
++ { PCI_VENDOR_ID_AMD, 0x1451 },
++};
++
++static bool cx23885_does_need_dma_reset(void)
++{
++ int i;
++ struct pci_dev *pdev = NULL;
++
++ if (dma_reset_workaround == 0)
++ return false;
++ else if (dma_reset_workaround == 2)
++ return true;
++
++ for (i = 0; i < ARRAY_SIZE(broken_dev_id); i++) {
++ pdev = pci_get_device(broken_dev_id[i].vendor,
++ broken_dev_id[i].dev, NULL);
++ if (pdev) {
++ pci_dev_put(pdev);
++ return true;
++ }
++ }
++ return false;
++}
++
+ static int cx23885_initdev(struct pci_dev *pci_dev,
+ const struct pci_device_id *pci_id)
+ {
+@@ -2069,6 +2118,8 @@ static int cx23885_initdev(struct pci_de
+ if (NULL == dev)
+ return -ENOMEM;
+
++ dev->need_dma_reset = cx23885_does_need_dma_reset();
++
+ err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
+ if (err < 0)
+ goto fail_free;
+--- a/drivers/media/pci/cx23885/cx23885.h
++++ b/drivers/media/pci/cx23885/cx23885.h
+@@ -451,6 +451,8 @@ struct cx23885_dev {
+ /* Analog raw audio */
+ struct cx23885_audio_dev *audio_dev;
+
++ /* Does the system require periodic DMA resets? */
++ unsigned int need_dma_reset:1;
+ };
+
+ static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
--- /dev/null
+From 0ae976a11b4fb5704b597e103b5189237641c1a1 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo.bianconi@redhat.com>
+Date: Thu, 6 Sep 2018 11:18:41 +0200
+Subject: mt76x0: init hw capabilities
+
+From: Lorenzo Bianconi <lorenzo.bianconi@redhat.com>
+
+commit 0ae976a11b4fb5704b597e103b5189237641c1a1 upstream.
+
+Enable hw capabilities supported by mt76-usb layer
+- fast_xmit
+- tx/rx amsdu
+- MFP
+- non-linear tx skbs
+
+[This is one line hw feature backport from 0ae976a11b4f ("mt76x0: init
+hw capabilities"), which add also other different features, however
+those are not supported in 4.19.
+
+802.11w is supported by mac80211 and mt76x0u driver in 4.19 correctly
+fall-back to software encryption when 802.11w ciphers are used.
+
+Without the patch we fail to associate with WPA3 APs, so this is
+considered as fix.]
+
+Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@redhat.com>
+Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com>
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+[remove marking non-working features on 4.19, make topic correspond the change]
+Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/wireless/mediatek/mt76/mt76x0/init.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/net/wireless/mediatek/mt76/mt76x0/init.c
++++ b/drivers/net/wireless/mediatek/mt76/mt76x0/init.c
+@@ -681,6 +681,7 @@ int mt76x0_register_device(struct mt76x0
+ ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
+ ieee80211_hw_set(hw, AMPDU_AGGREGATION);
+ ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
++ ieee80211_hw_set(hw, MFP_CAPABLE);
+ hw->max_rates = 1;
+ hw->max_report_rates = 7;
+ hw->max_rate_tries = 1;