phy: exynos5-usbdrd: fix MPLL_MULTIPLIER and SSC_REFCLKSEL masks in refclk

commit e2158c953c973adb49383ddea2504faf08d375b7 upstream.

In exynos5_usbdrd_{pipe3,utmi}_set_refclk(), the masks
PHYCLKRST_MPLL_MULTIPLIER_MASK and PHYCLKRST_SSC_REFCLKSEL_MASK are not
inverted when applied to the register values. Fix it.

Cc: stable@vger.kernel.org
Fixes: 59025887fb08 ("phy: Add new Exynos5 USB 3.0 PHY driver")
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250209-exynos5-usbdrd-masks-v1-1-4f7f83f323d7@disroot.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index ee0848fe8432473a63ff195e1825361bfb0f5cb9..ca6101ef6076200ed77da6c9dfa6b6f32c248720 100644 (file)
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -288,9 +288,9 @@ exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst)
        reg |=  PHYCLKRST_REFCLKSEL_EXT_REFCLK;
 
        /* FSEL settings corresponding to reference clock */
-       reg &= ~PHYCLKRST_FSEL_PIPE_MASK |
-               PHYCLKRST_MPLL_MULTIPLIER_MASK |
-               PHYCLKRST_SSC_REFCLKSEL_MASK;
+       reg &= ~(PHYCLKRST_FSEL_PIPE_MASK |
+                PHYCLKRST_MPLL_MULTIPLIER_MASK |
+                PHYCLKRST_SSC_REFCLKSEL_MASK);
        switch (phy_drd->extrefclk) {
        case EXYNOS5_FSEL_50MHZ:
                reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
@@ -332,9 +332,9 @@ exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst)
        reg &= ~PHYCLKRST_REFCLKSEL_MASK;
        reg |=  PHYCLKRST_REFCLKSEL_EXT_REFCLK;
 
-       reg &= ~PHYCLKRST_FSEL_UTMI_MASK |
-               PHYCLKRST_MPLL_MULTIPLIER_MASK |
-               PHYCLKRST_SSC_REFCLKSEL_MASK;
+       reg &= ~(PHYCLKRST_FSEL_UTMI_MASK |
+                PHYCLKRST_MPLL_MULTIPLIER_MASK |
+                PHYCLKRST_SSC_REFCLKSEL_MASK);
        reg |= PHYCLKRST_FSEL(phy_drd->extrefclk);
 
        return reg;