5.10-stable patches

added patches:
	drm-amdgpu-display-drop-dcn-support-for-aarch64.patch

diff --git a/queue-5.10/drm-amdgpu-display-drop-dcn-support-for-aarch64.patch b/queue-5.10/drm-amdgpu-display-drop-dcn-support-for-aarch64.patch
new file mode 100644 (file)
index 0000000..944e6fa
--- /dev/null
+++ b/queue-5.10/drm-amdgpu-display-drop-dcn-support-for-aarch64.patch
@@ -0,0 +1,304 @@
+From c241ed2f0ea549c18cff62a3708b43846b84dae3 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 4 Jan 2021 11:24:20 -0500
+Subject: drm/amdgpu/display: drop DCN support for aarch64
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit c241ed2f0ea549c18cff62a3708b43846b84dae3 upstream.
+
+From Ard:
+
+"Simply disabling -mgeneral-regs-only left and right is risky, given that
+the standard AArch64 ABI permits the use of FP/SIMD registers anywhere,
+and GCC is known to use SIMD registers for spilling, and may invent
+other uses of the FP/SIMD register file that have nothing to do with the
+floating point code in question. Note that putting kernel_neon_begin()
+and kernel_neon_end() around the code that does use FP is not sufficient
+here, the problem is in all the other code that may be emitted with
+references to SIMD registers in it.
+
+So the only way to do this properly is to put all floating point code in
+a separate compilation unit, and only compile that unit with
+-mgeneral-regs-only."
+
+Disable support until the code can be properly refactored to support this
+properly on aarch64.
+
+Acked-by: Will Deacon <will@kernel.org>
+Reported-by: Ard Biesheuvel <ardb@kernel.org>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+[ardb: backport to v5.10 by reverting c38d444e44badc55 instead]
+Acked-by: Alex Deucher <alexander.deucher@amd.com> # v5.10 backport
+Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/Kconfig                   |    2 
+ drivers/gpu/drm/amd/display/dc/calcs/Makefile         |    7 -
+ drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile       |    7 -
+ drivers/gpu/drm/amd/display/dc/dcn10/Makefile         |    7 -
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c |   81 ++++++------------
+ drivers/gpu/drm/amd/display/dc/dcn20/Makefile         |    4 
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile         |    4 
+ drivers/gpu/drm/amd/display/dc/dml/Makefile           |   13 --
+ drivers/gpu/drm/amd/display/dc/dsc/Makefile           |    5 -
+ drivers/gpu/drm/amd/display/dc/os_types.h             |    4 
+ 10 files changed, 32 insertions(+), 102 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/Kconfig
++++ b/drivers/gpu/drm/amd/display/Kconfig
+@@ -6,7 +6,7 @@ config DRM_AMD_DC
+       bool "AMD DC - Enable new display engine"
+       default y
+       select SND_HDA_COMPONENT if SND_HDA_CORE
+-      select DRM_AMD_DC_DCN if (X86 || PPC64 || (ARM64 && KERNEL_MODE_NEON)) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
++      select DRM_AMD_DC_DCN if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
+       help
+         Choose this option if you want to use the new display engine
+         support for AMDGPU. This adds required support for Vega and
+--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+@@ -33,10 +33,6 @@ ifdef CONFIG_PPC64
+ calcs_ccflags := -mhard-float -maltivec
+ endif
+ 
+-ifdef CONFIG_ARM64
+-calcs_rcflags := -mgeneral-regs-only
+-endif
+-
+ ifdef CONFIG_CC_IS_GCC
+ ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+ IS_OLD_GCC = 1
+@@ -57,9 +53,6 @@ endif
+ CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
+ CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags)
+ CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_math.o := $(calcs_ccflags) -Wno-tautological-compare
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_rcflags)
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_rcflags)
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/calcs/dcn_calc_math.o := $(calcs_rcflags)
+ 
+ BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o
+ 
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+@@ -104,13 +104,6 @@ ifdef CONFIG_PPC64
+ CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)
+ endif
+ 
+-# prevent build errors:
+-# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types
+-# this file is unused on arm64, just like on ppc64
+-ifdef CONFIG_ARM64
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := -mgeneral-regs-only
+-endif
+-
+ AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DCN21))
+ 
+ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21)
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
+@@ -31,11 +31,4 @@ DCN10 = dcn10_init.o dcn10_resource.o dc
+ 
+ AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
+ 
+-# fix:
+-# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types
+-# aarch64 does not support soft-float, so use hard-float and handle this in code
+-ifdef CONFIG_ARM64
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn10/dcn10_resource.o := -mgeneral-regs-only
+-endif
+-
+ AMD_DISPLAY_FILES += $(AMD_DAL_DCN10)
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -1339,47 +1339,6 @@ static uint32_t read_pipe_fuses(struct d
+       return value;
+ }
+ 
+-/*
+- * Some architectures don't support soft-float (e.g. aarch64), on those
+- * this function has to be called with hardfloat enabled, make sure not
+- * to inline it so whatever fp stuff is done stays inside
+- */
+-static noinline void dcn10_resource_construct_fp(
+-      struct dc *dc)
+-{
+-      if (dc->ctx->dce_version == DCN_VERSION_1_01) {
+-              struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
+-              struct dcn_ip_params *dcn_ip = dc->dcn_ip;
+-              struct display_mode_lib *dml = &dc->dml;
+-
+-              dml->ip.max_num_dpp = 3;
+-              /* TODO how to handle 23.84? */
+-              dcn_soc->dram_clock_change_latency = 23;
+-              dcn_ip->max_num_dpp = 3;
+-      }
+-      if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
+-              dc->dcn_soc->urgent_latency = 3;
+-              dc->debug.disable_dmcu = true;
+-              dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
+-      }
+-
+-
+-      dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
+-      ASSERT(dc->dcn_soc->number_of_channels < 3);
+-      if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/
+-              dc->dcn_soc->number_of_channels = 2;
+-
+-      if (dc->dcn_soc->number_of_channels == 1) {
+-              dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
+-              dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
+-              dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
+-              dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
+-              if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
+-                      dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
+-              }
+-      }
+-}
+-
+ static bool dcn10_resource_construct(
+       uint8_t num_virtual_links,
+       struct dc *dc,
+@@ -1531,15 +1490,37 @@ static bool dcn10_resource_construct(
+       memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
+       memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
+ 
+-#if defined(CONFIG_ARM64)
+-      /* Aarch64 does not support -msoft-float/-mfloat-abi=soft */
+-      DC_FP_START();
+-      dcn10_resource_construct_fp(dc);
+-      DC_FP_END();
+-#else
+-      /* Other architectures we build for build this with soft-float */
+-      dcn10_resource_construct_fp(dc);
+-#endif
++      if (dc->ctx->dce_version == DCN_VERSION_1_01) {
++              struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
++              struct dcn_ip_params *dcn_ip = dc->dcn_ip;
++              struct display_mode_lib *dml = &dc->dml;
++
++              dml->ip.max_num_dpp = 3;
++              /* TODO how to handle 23.84? */
++              dcn_soc->dram_clock_change_latency = 23;
++              dcn_ip->max_num_dpp = 3;
++      }
++      if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
++              dc->dcn_soc->urgent_latency = 3;
++              dc->debug.disable_dmcu = true;
++              dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
++      }
++
++
++      dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
++      ASSERT(dc->dcn_soc->number_of_channels < 3);
++      if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/
++              dc->dcn_soc->number_of_channels = 2;
++
++      if (dc->dcn_soc->number_of_channels == 1) {
++              dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
++              dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
++              dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
++              dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
++              if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
++                      dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
++              }
++      }
+ 
+       pool->base.pp_smu = dcn10_pp_smu_create(ctx);
+ 
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+@@ -17,10 +17,6 @@ ifdef CONFIG_PPC64
+ CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -maltivec
+ endif
+ 
+-ifdef CONFIG_ARM64
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mgeneral-regs-only
+-endif
+-
+ ifdef CONFIG_CC_IS_GCC
+ ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+ IS_OLD_GCC = 1
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -13,10 +13,6 @@ ifdef CONFIG_PPC64
+ CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -maltivec
+ endif
+ 
+-ifdef CONFIG_ARM64
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mgeneral-regs-only
+-endif
+-
+ ifdef CONFIG_CC_IS_GCC
+ ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+ IS_OLD_GCC = 1
+--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+@@ -33,10 +33,6 @@ ifdef CONFIG_PPC64
+ dml_ccflags := -mhard-float -maltivec
+ endif
+ 
+-ifdef CONFIG_ARM64
+-dml_rcflags := -mgeneral-regs-only
+-endif
+-
+ ifdef CONFIG_CC_IS_GCC
+ ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+ IS_OLD_GCC = 1
+@@ -64,13 +60,6 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/displa
+ CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
+ CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags)
+ CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_rcflags)
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_rcflags)
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_rcflags)
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_rcflags)
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_rcflags)
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_rcflags)
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_rcflags)
+ endif
+ ifdef CONFIG_DRM_AMD_DC_DCN3_0
+ CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_ccflags) -Wframe-larger-than=2048
+@@ -78,8 +67,6 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/displa
+ endif
+ CFLAGS_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_ccflags)
+ CFLAGS_$(AMDDALPATH)/dc/dml/display_rq_dlg_helpers.o := $(dml_ccflags)
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_rcflags)
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_rq_dlg_helpers.o := $(dml_rcflags)
+ 
+ DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
+ 
+--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+@@ -10,10 +10,6 @@ ifdef CONFIG_PPC64
+ dsc_ccflags := -mhard-float -maltivec
+ endif
+ 
+-ifdef CONFIG_ARM64
+-dsc_rcflags := -mgeneral-regs-only
+-endif
+-
+ ifdef CONFIG_CC_IS_GCC
+ ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+ IS_OLD_GCC = 1
+@@ -32,7 +28,6 @@ endif
+ endif
+ 
+ CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_ccflags)
+-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_rcflags)
+ 
+ DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o
+ 
+--- a/drivers/gpu/drm/amd/display/dc/os_types.h
++++ b/drivers/gpu/drm/amd/display/dc/os_types.h
+@@ -55,10 +55,6 @@
+ #include <asm/fpu/api.h>
+ #define DC_FP_START() kernel_fpu_begin()
+ #define DC_FP_END() kernel_fpu_end()
+-#elif defined(CONFIG_ARM64)
+-#include <asm/neon.h>
+-#define DC_FP_START() kernel_neon_begin()
+-#define DC_FP_END() kernel_neon_end()
+ #elif defined(CONFIG_PPC64)
+ #include <asm/switch_to.h>
+ #include <asm/cputable.h>

diff --git a/queue-5.10/series b/queue-5.10/series
index 196854e37bc87a757bb5cb673a44fb087ddd4803..5eeab8fe3dd437c94c0c4c10a3843724927a0f34 100644 (file)
--- a/queue-5.10/series
+++ b/queue-5.10/series
@@ -1,3 +1,4 @@
 revert-kconfig-remove-kvmconfig-and-xenconfig-shorthands.patch
 bpf-fix-selftest-compilation-on-clang-11.patch
 x86-hyperv-initialize-clockevents-after-lapic-is-ini.patch
+drm-amdgpu-display-drop-dcn-support-for-aarch64.patch

diff --git a/queue-5.10/x86-hyperv-initialize-clockevents-after-lapic-is-ini.patch b/queue-5.10/x86-hyperv-initialize-clockevents-after-lapic-is-ini.patch
index a8de60662b93743cfa7be2e1034170e53bf8e3b5..190a263f3cacf7c6df4a3127e3e7a23591c45880 100644 (file)
--- a/queue-5.10/x86-hyperv-initialize-clockevents-after-lapic-is-ini.patch
+++ b/queue-5.10/x86-hyperv-initialize-clockevents-after-lapic-is-ini.patch
@@ -58,14 +58,12 @@ Link: https://lore.kernel.org/r/20210116223136.13892-1-decui@microsoft.com
 Signed-off-by: Wei Liu <wei.liu@kernel.org>
 Signed-off-by: Sasha Levin <sashal@kernel.org>
 ---
- arch/x86/hyperv/hv_init.c | 29 ++++++++++++++++++++++++++---
+ arch/x86/hyperv/hv_init.c |   29 ++++++++++++++++++++++++++---
  1 file changed, 26 insertions(+), 3 deletions(-)
 
-diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c
-index e04d90af4c27c..6fb8cb7b9bcc6 100644
 --- a/arch/x86/hyperv/hv_init.c
 +++ b/arch/x86/hyperv/hv_init.c
-@@ -312,6 +312,25 @@ static struct syscore_ops hv_syscore_ops = {
+@@ -312,6 +312,25 @@ static struct syscore_ops hv_syscore_ops
        .resume         = hv_resume,
  };
  
@@ -109,6 +107,3 @@ index e04d90af4c27c..6fb8cb7b9bcc6 100644
  
        hv_apic_init();
  
--- 
-2.27.0
-