drm/msm: Update GMU register xml

Update GMU register xml with additional definitions for a7x family.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673356/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
index 3d2cc339b8f19c8d24b2c9144569b2364afc5ebc..b15a242d974d6b42133171c8484d3b0413f2d3a4 100644 (file)
--- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
@@ -99,6 +99,10 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
                <bitfield name="GX_HM_GDSC_POWER_OFF" pos="6" type="boolean"/>
                <bitfield name="GX_HM_CLK_OFF" pos="7" type="boolean"/>
        </reg32>
+       <reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A7XX">
+               <bitfield name="GX_HM_GDSC_POWER_OFF" pos="0" type="boolean"/>
+               <bitfield name="GX_HM_CLK_OFF" pos="1" type="boolean"/>
+       </reg32>
        <reg32 offset="0x50e4" name="GMU_GPU_NAP_CTRL">
                <bitfield name="HW_NAP_ENABLE" pos="0"/>
                <bitfield name="SID" low="4" high="8"/>
@@ -127,6 +131,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
        <reg32 offset="0x5088" name="GMU_ALWAYS_ON_COUNTER_L"/>
        <reg32 offset="0x5089" name="GMU_ALWAYS_ON_COUNTER_H"/>
        <reg32 offset="0x50c3" name="GMU_GMU_PWR_COL_KEEPALIVE"/>
+       <reg32 offset="0x50c4" name="GMU_PWR_COL_PREEMPT_KEEPALIVE"/>
        <reg32 offset="0x5180" name="GMU_HFI_CTRL_STATUS"/>
        <reg32 offset="0x5181" name="GMU_HFI_VERSION_INFO"/>
        <reg32 offset="0x5182" name="GMU_HFI_SFR_ADDR"/>
@@ -228,6 +233,12 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
        <reg32 offset="0x03ee" name="RSCC_TCS1_DRV0_STATUS"/>
        <reg32 offset="0x0496" name="RSCC_TCS2_DRV0_STATUS"/>
        <reg32 offset="0x053e" name="RSCC_TCS3_DRV0_STATUS"/>
+       <reg32 offset="0x05e6" name="RSCC_TCS4_DRV0_STATUS" variants="A7XX"/>
+       <reg32 offset="0x068e" name="RSCC_TCS5_DRV0_STATUS" variants="A7XX"/>
+       <reg32 offset="0x0736" name="RSCC_TCS6_DRV0_STATUS" variants="A7XX"/>
+       <reg32 offset="0x07de" name="RSCC_TCS7_DRV0_STATUS" variants="A7XX"/>
+       <reg32 offset="0x0886" name="RSCC_TCS8_DRV0_STATUS" variants="A7XX"/>
+       <reg32 offset="0x092e" name="RSCC_TCS9_DRV0_STATUS" variants="A7XX"/>
 </domain>
 
 </database>