rs6000.md (floatsidf2): Rewrite PowerPC64 case to use gen_floatdidf2 directly.

2008-09-15  Andrew Pinski  <andrew_pinski@playstation.sony.com>

        * config/rs6000/rs6000.md (floatsidf2): Rewrite PowerPC64 case to
        use gen_floatdidf2 directly.
        (floatunssidf2): Likewise.
        (floatsidf_ppc64_mfpgpr): Remove.
        (floatsidf_ppc64): Remove.
        (floatunssidf_ppc64): Remove.

From-SVN: r140381

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 31660347522ea30d9fea1a3eaa5dc0ed2da40185..4deb997cc15ed446e63f20b9c199d541c4103264 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2008-09-15  Andrew Pinski  <andrew_pinski@playstation.sony.com>
+
+       * config/rs6000/rs6000.md (floatsidf2): Rewrite PowerPC64 case to
+       use gen_floatdidf2 directly.
+       (floatunssidf2): Likewise.
+       (floatsidf_ppc64_mfpgpr): Remove.
+       (floatsidf_ppc64): Remove.
+       (floatunssidf_ppc64): Remove.
+
 2008-09-15  Jakub Jelinek  <jakub@redhat.com>
 
        * ira-color.c (finish_cost_update): Free update_cost_queue_elems

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 8fe16464285dcd8a357500e3b431402d41c320e5..d35e9d4eac205f74b646afe1dca8b3b05586c03f 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5828,18 +5828,10 @@
       emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
       DONE;
     }
-  if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS)
-    {
-      rtx t1 = gen_reg_rtx (DImode);
-      emit_insn (gen_floatsidf_ppc64_mfpgpr (operands[0], operands[1], t1));
-      DONE;
-    }
   if (TARGET_POWERPC64)
     {
-      rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
-      rtx t1 = gen_reg_rtx (DImode);
-      rtx t2 = gen_reg_rtx (DImode);
-      emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
+      rtx x = convert_to_mode (DImode, operands[1], 0);
+      emit_insn (gen_floatdidf2 (operands[0], x));
       DONE;
     }
 
@@ -5907,11 +5899,8 @@
     }
   if (TARGET_POWERPC64)
     {
-      rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
-      rtx t1 = gen_reg_rtx (DImode);
-      rtx t2 = gen_reg_rtx (DImode);
-      emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
-                                        t1, t2));
+      rtx x = convert_to_mode (DImode, operands[1], 1);
+      emit_insn (gen_floatdidf2 (operands[0], x));
       DONE;
     }
 
@@ -6132,47 +6121,6 @@
   "fcfid %0,%1"
   [(set_attr "type" "fp")])
 
-(define_insn_and_split "floatsidf_ppc64_mfpgpr"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-       (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
-   (clobber (match_operand:DI 2 "gpc_reg_operand" "=r"))]
-  "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
-  "#"
-  "&& 1"
-  [(set (match_dup 2) (sign_extend:DI (match_dup 1)))
-   (set (match_dup 0) (float:DF (match_dup 2)))]
-  "")
-
-(define_insn_and_split "floatsidf_ppc64"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-       (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
-   (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))
-   (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
-   (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
-  "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
-  "#"
-  "&& 1"
-  [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
-   (set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (match_dup 2))
-   (set (match_dup 0) (float:DF (match_dup 4)))]
-  "")
-
-(define_insn_and_split "floatunssidf_ppc64"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-       (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
-   (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))
-   (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
-   (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
-  "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
-  "#"
-  "&& 1"
-  [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
-   (set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (match_dup 2))
-   (set (match_dup 0) (float:DF (match_dup 4)))]
-  "")
-
 (define_insn "fix_truncdfdi2"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r")
        (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]