--- /dev/null
+From 13888d78c664a1f61d7b09d282f5916993827a40 Mon Sep 17 00:00:00 2001
+From: Paulo Zanoni <paulo.r.zanoni@intel.com>
+Date: Tue, 20 Nov 2012 13:27:41 -0200
+Subject: drm/i915: make the panel fitter work on pipes B and C on IVB
+
+From: Paulo Zanoni <paulo.r.zanoni@intel.com>
+
+commit 13888d78c664a1f61d7b09d282f5916993827a40 upstream.
+
+I actually found this problem on Haswell, but then discovered Ivy
+Bridge also has it by reading the spec.
+
+I don't have the hardware to test this.
+
+Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
+Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_reg.h | 2 ++
+ drivers/gpu/drm/i915/intel_display.c | 6 +++++-
+ 2 files changed, 7 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -3315,6 +3315,8 @@
+ #define _PFA_CTL_1 0x68080
+ #define _PFB_CTL_1 0x68880
+ #define PF_ENABLE (1<<31)
++#define PF_PIPE_SEL_MASK_IVB (3<<29)
++#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
+ #define PF_FILTER_MASK (3<<23)
+ #define PF_FILTER_PROGRAMMED (0<<23)
+ #define PF_FILTER_MED_3x3 (1<<23)
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -3225,7 +3225,11 @@ static void ironlake_crtc_enable(struct
+ * as some pre-programmed values are broken,
+ * e.g. x201.
+ */
+- I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
++ if (IS_IVYBRIDGE(dev))
++ I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
++ PF_PIPE_SEL_IVB(pipe));
++ else
++ I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
+ I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
+ I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
+ }
--- /dev/null
+From eda85d6ad490923152544fba0473798b6cc0edf6 Mon Sep 17 00:00:00 2001
+From: Aaro Koskinen <aaro.koskinen@iki.fi>
+Date: Mon, 31 Dec 2012 03:34:59 +0200
+Subject: drm/nouveau: fix init with agpgart-uninorth
+
+From: Aaro Koskinen <aaro.koskinen@iki.fi>
+
+commit eda85d6ad490923152544fba0473798b6cc0edf6 upstream.
+
+Check that the AGP aperture can be mapped. This follows a similar change
+done for Radeon (commit 365048ff, drm/radeon: AGP memory is only I/O if
+the aperture can be mapped by the CPU.).
+
+The patch fixes the following error seen on G5 iMac:
+
+ nouveau E[ DRM] failed to create kernel channel, -12
+
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58806
+Reviewed-by: Michel Dänzer <michel@daenzer.net>
+Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/nouveau/nouveau_bo.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
++++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
+@@ -1279,7 +1279,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo
+ if (drm->agp.stat == ENABLED) {
+ mem->bus.offset = mem->start << PAGE_SHIFT;
+ mem->bus.base = drm->agp.base;
+- mem->bus.is_iomem = true;
++ mem->bus.is_iomem = !dev->agp->cant_use_aperture;
+ }
+ #endif
+ break;
--- /dev/null
+From cafa59b9011a7790be4ddd5979419259844a165d Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 20 Dec 2012 16:35:47 -0500
+Subject: drm/radeon: add connector table for Mac G4 Silver
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit cafa59b9011a7790be4ddd5979419259844a165d upstream.
+
+Apple cards do not provide data tables in the vbios
+so we have to hard code the connector parameters
+in the driver.
+
+Reported-by: Albrecht Dreß <albrecht.dress@arcor.de>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_combios.c | 51 ++++++++++++++++++++++++++++++++
+ drivers/gpu/drm/radeon/radeon_mode.h | 3 +
+ 2 files changed, 53 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_combios.c
++++ b/drivers/gpu/drm/radeon/radeon_combios.c
+@@ -1548,6 +1548,9 @@ bool radeon_get_legacy_connector_info_fr
+ of_machine_is_compatible("PowerBook6,7")) {
+ /* ibook */
+ rdev->mode_info.connector_table = CT_IBOOK;
++ } else if (of_machine_is_compatible("PowerMac3,5")) {
++ /* PowerMac G4 Silver radeon 7500 */
++ rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
+ } else if (of_machine_is_compatible("PowerMac4,4")) {
+ /* emac */
+ rdev->mode_info.connector_table = CT_EMAC;
+@@ -2210,6 +2213,54 @@ bool radeon_get_legacy_connector_info_fr
+ DRM_MODE_CONNECTOR_SVIDEO,
+ &ddc_i2c,
+ CONNECTOR_OBJECT_ID_SVIDEO,
++ &hpd);
++ break;
++ case CT_MAC_G4_SILVER:
++ DRM_INFO("Connector Table: %d (mac g4 silver)\n",
++ rdev->mode_info.connector_table);
++ /* DVI-I - tv dac, int tmds */
++ ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
++ hpd.hpd = RADEON_HPD_1; /* ??? */
++ radeon_add_legacy_encoder(dev,
++ radeon_get_encoder_enum(dev,
++ ATOM_DEVICE_DFP1_SUPPORT,
++ 0),
++ ATOM_DEVICE_DFP1_SUPPORT);
++ radeon_add_legacy_encoder(dev,
++ radeon_get_encoder_enum(dev,
++ ATOM_DEVICE_CRT2_SUPPORT,
++ 2),
++ ATOM_DEVICE_CRT2_SUPPORT);
++ radeon_add_legacy_connector(dev, 0,
++ ATOM_DEVICE_DFP1_SUPPORT |
++ ATOM_DEVICE_CRT2_SUPPORT,
++ DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
++ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
++ &hpd);
++ /* VGA - primary dac */
++ ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
++ hpd.hpd = RADEON_HPD_NONE;
++ radeon_add_legacy_encoder(dev,
++ radeon_get_encoder_enum(dev,
++ ATOM_DEVICE_CRT1_SUPPORT,
++ 1),
++ ATOM_DEVICE_CRT1_SUPPORT);
++ radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
++ DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
++ CONNECTOR_OBJECT_ID_VGA,
++ &hpd);
++ /* TV - TV DAC */
++ ddc_i2c.valid = false;
++ hpd.hpd = RADEON_HPD_NONE;
++ radeon_add_legacy_encoder(dev,
++ radeon_get_encoder_enum(dev,
++ ATOM_DEVICE_TV1_SUPPORT,
++ 2),
++ ATOM_DEVICE_TV1_SUPPORT);
++ radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
++ DRM_MODE_CONNECTOR_SVIDEO,
++ &ddc_i2c,
++ CONNECTOR_OBJECT_ID_SVIDEO,
+ &hpd);
+ break;
+ default:
+--- a/drivers/gpu/drm/radeon/radeon_mode.h
++++ b/drivers/gpu/drm/radeon/radeon_mode.h
+@@ -209,7 +209,8 @@ enum radeon_connector_table {
+ CT_RN50_POWER,
+ CT_MAC_X800,
+ CT_MAC_G5_9600,
+- CT_SAM440EP
++ CT_SAM440EP,
++ CT_MAC_G4_SILVER
+ };
+
+ enum radeon_dvo_chip {
--- /dev/null
+From 668bbc81baf0f34df832d8aca5c7d5e19a493c68 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 20 Dec 2012 21:19:32 -0500
+Subject: drm/radeon: add WAIT_UNTIL to evergreen VM safe reg list
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 668bbc81baf0f34df832d8aca5c7d5e19a493c68 upstream.
+
+It's used in a recent mesa commit:
+http://cgit.freedesktop.org/mesa/mesa/commit/?id=24b1206ab2dcd506aaac3ef656aebc8bc20cd27a
+and there may be some other cases in the future where it's required.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Jerome Glisse <jglisse@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/evergreen_cs.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/gpu/drm/radeon/evergreen_cs.c
++++ b/drivers/gpu/drm/radeon/evergreen_cs.c
+@@ -2724,6 +2724,7 @@ static bool evergreen_vm_reg_valid(u32 r
+
+ /* check config regs */
+ switch (reg) {
++ case WAIT_UNTIL:
+ case GRBM_GFX_INDEX:
+ case CP_STRMOUT_CNTL:
+ case CP_COHER_CNTL:
--- /dev/null
+From 5f8f635edd8ad5a6416bff4c5ff486500357f473 Mon Sep 17 00:00:00 2001
+From: Jerome Glisse <jglisse@redhat.com>
+Date: Mon, 17 Dec 2012 11:04:32 -0500
+Subject: drm/radeon: avoid deadlock in pm path when waiting for fence
+
+From: Jerome Glisse <jglisse@redhat.com>
+
+commit 5f8f635edd8ad5a6416bff4c5ff486500357f473 upstream.
+
+radeon_fence_wait_empty_locked should not trigger GPU reset as no
+place where it's call from would benefit from such thing and it
+actually lead to a kernel deadlock in case the reset is triggered
+from pm codepath. Instead force ring completion in place where it
+makes sense or return early in others.
+
+Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon.h | 2 +-
+ drivers/gpu/drm/radeon/radeon_device.c | 13 +++++++++++--
+ drivers/gpu/drm/radeon/radeon_fence.c | 30 ++++++++++++++----------------
+ drivers/gpu/drm/radeon/radeon_pm.c | 15 ++++++++++++---
+ 4 files changed, 38 insertions(+), 22 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/radeon.h
++++ b/drivers/gpu/drm/radeon/radeon.h
+@@ -226,7 +226,7 @@ void radeon_fence_process(struct radeon_
+ bool radeon_fence_signaled(struct radeon_fence *fence);
+ int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
+ int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
+-void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
++int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
+ int radeon_fence_wait_any(struct radeon_device *rdev,
+ struct radeon_fence **fences,
+ bool intr);
+--- a/drivers/gpu/drm/radeon/radeon_device.c
++++ b/drivers/gpu/drm/radeon/radeon_device.c
+@@ -1163,6 +1163,7 @@ int radeon_suspend_kms(struct drm_device
+ struct drm_crtc *crtc;
+ struct drm_connector *connector;
+ int i, r;
++ bool force_completion = false;
+
+ if (dev == NULL || dev->dev_private == NULL) {
+ return -ENODEV;
+@@ -1205,8 +1206,16 @@ int radeon_suspend_kms(struct drm_device
+
+ mutex_lock(&rdev->ring_lock);
+ /* wait for gpu to finish processing current batch */
+- for (i = 0; i < RADEON_NUM_RINGS; i++)
+- radeon_fence_wait_empty_locked(rdev, i);
++ for (i = 0; i < RADEON_NUM_RINGS; i++) {
++ r = radeon_fence_wait_empty_locked(rdev, i);
++ if (r) {
++ /* delay GPU reset to resume */
++ force_completion = true;
++ }
++ }
++ if (force_completion) {
++ radeon_fence_driver_force_completion(rdev);
++ }
+ mutex_unlock(&rdev->ring_lock);
+
+ radeon_save_bios_scratch_regs(rdev);
+--- a/drivers/gpu/drm/radeon/radeon_fence.c
++++ b/drivers/gpu/drm/radeon/radeon_fence.c
+@@ -609,26 +609,20 @@ int radeon_fence_wait_next_locked(struct
+ * Returns 0 if the fences have passed, error for all other cases.
+ * Caller must hold ring lock.
+ */
+-void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring)
++int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring)
+ {
+ uint64_t seq = rdev->fence_drv[ring].sync_seq[ring];
++ int r;
+
+- while(1) {
+- int r;
+- r = radeon_fence_wait_seq(rdev, seq, ring, false, false);
++ r = radeon_fence_wait_seq(rdev, seq, ring, false, false);
++ if (r) {
+ if (r == -EDEADLK) {
+- mutex_unlock(&rdev->ring_lock);
+- r = radeon_gpu_reset(rdev);
+- mutex_lock(&rdev->ring_lock);
+- if (!r)
+- continue;
+- }
+- if (r) {
+- dev_err(rdev->dev, "error waiting for ring to become"
+- " idle (%d)\n", r);
++ return -EDEADLK;
+ }
+- return;
++ dev_err(rdev->dev, "error waiting for ring[%d] to become idle (%d)\n",
++ ring, r);
+ }
++ return 0;
+ }
+
+ /**
+@@ -854,13 +848,17 @@ int radeon_fence_driver_init(struct rade
+ */
+ void radeon_fence_driver_fini(struct radeon_device *rdev)
+ {
+- int ring;
++ int ring, r;
+
+ mutex_lock(&rdev->ring_lock);
+ for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
+ if (!rdev->fence_drv[ring].initialized)
+ continue;
+- radeon_fence_wait_empty_locked(rdev, ring);
++ r = radeon_fence_wait_empty_locked(rdev, ring);
++ if (r) {
++ /* no need to trigger GPU reset as we are unloading */
++ radeon_fence_driver_force_completion(rdev);
++ }
+ wake_up_all(&rdev->fence_queue);
+ radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
+ rdev->fence_drv[ring].initialized = false;
+--- a/drivers/gpu/drm/radeon/radeon_pm.c
++++ b/drivers/gpu/drm/radeon/radeon_pm.c
+@@ -234,7 +234,7 @@ static void radeon_set_power_state(struc
+
+ static void radeon_pm_set_clocks(struct radeon_device *rdev)
+ {
+- int i;
++ int i, r;
+
+ /* no need to take locks, etc. if nothing's going to change */
+ if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
+@@ -248,8 +248,17 @@ static void radeon_pm_set_clocks(struct
+ /* wait for the rings to drain */
+ for (i = 0; i < RADEON_NUM_RINGS; i++) {
+ struct radeon_ring *ring = &rdev->ring[i];
+- if (ring->ready)
+- radeon_fence_wait_empty_locked(rdev, i);
++ if (!ring->ready) {
++ continue;
++ }
++ r = radeon_fence_wait_empty_locked(rdev, i);
++ if (r) {
++ /* needs a GPU reset dont reset here */
++ mutex_unlock(&rdev->ring_lock);
++ up_write(&rdev->pm.mclk_lock);
++ mutex_unlock(&rdev->ddev->struct_mutex);
++ return;
++ }
+ }
+
+ radeon_unmap_vram_bos(rdev);
--- /dev/null
+From a02dc74b317d78298cb0587b9b1f6f741fd5c139 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 13 Nov 2012 18:03:41 -0500
+Subject: drm/radeon/dce32+: use fractional fb dividers for high clocks
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit a02dc74b317d78298cb0587b9b1f6f741fd5c139 upstream.
+
+Fixes flickering with some high res montiors.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/atombios_crtc.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/atombios_crtc.c
++++ b/drivers/gpu/drm/radeon/atombios_crtc.c
+@@ -561,6 +561,8 @@ static u32 atombios_adjust_pll(struct dr
+ /* use frac fb div on APUs */
+ if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
+ radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
++ if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
++ radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
+ } else {
+ radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
+
--- /dev/null
+From 76903b96adbfbb38b049765add21e02e44c387a5 Mon Sep 17 00:00:00 2001
+From: Jerome Glisse <jglisse@redhat.com>
+Date: Mon, 17 Dec 2012 10:29:06 -0500
+Subject: drm/radeon: don't leave fence blocked process on failed GPU reset
+
+From: Jerome Glisse <jglisse@redhat.com>
+
+commit 76903b96adbfbb38b049765add21e02e44c387a5 upstream.
+
+Force all fence to signal if GPU reset failed so no process get stuck
+on waiting fence.
+
+Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon.h | 1 +
+ drivers/gpu/drm/radeon/radeon_device.c | 1 +
+ drivers/gpu/drm/radeon/radeon_fence.c | 19 +++++++++++++++++++
+ 3 files changed, 21 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/radeon.h
++++ b/drivers/gpu/drm/radeon/radeon.h
+@@ -220,6 +220,7 @@ struct radeon_fence {
+ int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
+ int radeon_fence_driver_init(struct radeon_device *rdev);
+ void radeon_fence_driver_fini(struct radeon_device *rdev);
++void radeon_fence_driver_force_completion(struct radeon_device *rdev);
+ int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
+ void radeon_fence_process(struct radeon_device *rdev, int ring);
+ bool radeon_fence_signaled(struct radeon_fence *fence);
+--- a/drivers/gpu/drm/radeon/radeon_device.c
++++ b/drivers/gpu/drm/radeon/radeon_device.c
+@@ -1356,6 +1356,7 @@ retry:
+ }
+ }
+ } else {
++ radeon_fence_driver_force_completion(rdev);
+ for (i = 0; i < RADEON_NUM_RINGS; ++i) {
+ kfree(ring_data[i]);
+ }
+--- a/drivers/gpu/drm/radeon/radeon_fence.c
++++ b/drivers/gpu/drm/radeon/radeon_fence.c
+@@ -868,6 +868,25 @@ void radeon_fence_driver_fini(struct rad
+ mutex_unlock(&rdev->ring_lock);
+ }
+
++/**
++ * radeon_fence_driver_force_completion - force all fence waiter to complete
++ *
++ * @rdev: radeon device pointer
++ *
++ * In case of GPU reset failure make sure no process keep waiting on fence
++ * that will never complete.
++ */
++void radeon_fence_driver_force_completion(struct radeon_device *rdev)
++{
++ int ring;
++
++ for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
++ if (!rdev->fence_drv[ring].initialized)
++ continue;
++ radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);
++ }
++}
++
+
+ /*
+ * Fence debugfs
--- /dev/null
+From bd25f0783dc3fb72e1e2779c2b99b2d34b67fa8a Mon Sep 17 00:00:00 2001
+From: Jerome Glisse <jglisse@redhat.com>
+Date: Tue, 11 Dec 2012 11:56:52 -0500
+Subject: drm/radeon: fix amd afusion gpu setup aka sumo v2
+
+From: Jerome Glisse <jglisse@redhat.com>
+
+commit bd25f0783dc3fb72e1e2779c2b99b2d34b67fa8a upstream.
+
+Set the proper number of tile pipe that should be a multiple of
+pipe depending on the number of se engine.
+
+Fix:
+https://bugs.freedesktop.org/show_bug.cgi?id=56405
+https://bugs.freedesktop.org/show_bug.cgi?id=56720
+
+v2: Don't change sumo2
+
+Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/evergreen.c | 8 ++++----
+ drivers/gpu/drm/radeon/evergreend.h | 2 ++
+ 2 files changed, 6 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/evergreen.c
++++ b/drivers/gpu/drm/radeon/evergreen.c
+@@ -1821,7 +1821,7 @@ static void evergreen_gpu_init(struct ra
+ case CHIP_SUMO:
+ rdev->config.evergreen.num_ses = 1;
+ rdev->config.evergreen.max_pipes = 4;
+- rdev->config.evergreen.max_tile_pipes = 2;
++ rdev->config.evergreen.max_tile_pipes = 4;
+ if (rdev->pdev->device == 0x9648)
+ rdev->config.evergreen.max_simds = 3;
+ else if ((rdev->pdev->device == 0x9647) ||
+@@ -1844,7 +1844,7 @@ static void evergreen_gpu_init(struct ra
+ rdev->config.evergreen.sc_prim_fifo_size = 0x40;
+ rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
+ rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+- gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
++ gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN;
+ break;
+ case CHIP_SUMO2:
+ rdev->config.evergreen.num_ses = 1;
+@@ -1866,7 +1866,7 @@ static void evergreen_gpu_init(struct ra
+ rdev->config.evergreen.sc_prim_fifo_size = 0x40;
+ rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
+ rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+- gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
++ gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN;
+ break;
+ case CHIP_BARTS:
+ rdev->config.evergreen.num_ses = 2;
+@@ -1914,7 +1914,7 @@ static void evergreen_gpu_init(struct ra
+ break;
+ case CHIP_CAICOS:
+ rdev->config.evergreen.num_ses = 1;
+- rdev->config.evergreen.max_pipes = 4;
++ rdev->config.evergreen.max_pipes = 2;
+ rdev->config.evergreen.max_tile_pipes = 2;
+ rdev->config.evergreen.max_simds = 2;
+ rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
+--- a/drivers/gpu/drm/radeon/evergreend.h
++++ b/drivers/gpu/drm/radeon/evergreend.h
+@@ -45,6 +45,8 @@
+ #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002
+ #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001
+ #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001
++#define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002
++#define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002
+
+ /* Registers */
+
--- /dev/null
+From 93927f9c1db5f55085457e820f0631064c7bfa34 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 4 Dec 2012 16:50:28 -0500
+Subject: drm/radeon: fix eDP clk and lane setup for scaled modes
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 93927f9c1db5f55085457e820f0631064c7bfa34 upstream.
+
+Need to use the adjusted mode since we are sending native
+timing and using the scaler for non-native modes.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Jerome Glisse <jglisse@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/atombios_encoders.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/atombios_encoders.c
++++ b/drivers/gpu/drm/radeon/atombios_encoders.c
+@@ -340,7 +340,7 @@ static bool radeon_atom_mode_fixup(struc
+ ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
+ (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
+ struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
+- radeon_dp_set_link_config(connector, mode);
++ radeon_dp_set_link_config(connector, adjusted_mode);
+ }
+
+ return true;
--- /dev/null
+From 0a9069d34918659bc8a89e21e69e60b2b83291a3 Mon Sep 17 00:00:00 2001
+From: Niels Ole Salscheider <niels_ole@salscheider-online.de>
+Date: Thu, 3 Jan 2013 19:09:28 +0100
+Subject: drm/radeon: Properly handle DDC probe for DP bridges
+
+From: Niels Ole Salscheider <niels_ole@salscheider-online.de>
+
+commit 0a9069d34918659bc8a89e21e69e60b2b83291a3 upstream.
+
+DDC information can be accessed using AUX CH
+
+Fixes failure to probe monitors on some systems with
+DP bridge chips.
+
+agd5f: minor fixes
+
+Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_connectors.c | 10 ++++++----
+ drivers/gpu/drm/radeon/radeon_display.c | 13 +++++++++----
+ drivers/gpu/drm/radeon/radeon_i2c.c | 10 ++++++++--
+ drivers/gpu/drm/radeon/radeon_mode.h | 2 +-
+ 4 files changed, 24 insertions(+), 11 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_connectors.c
++++ b/drivers/gpu/drm/radeon/radeon_connectors.c
+@@ -741,7 +741,7 @@ radeon_vga_detect(struct drm_connector *
+ ret = connector_status_disconnected;
+
+ if (radeon_connector->ddc_bus)
+- dret = radeon_ddc_probe(radeon_connector);
++ dret = radeon_ddc_probe(radeon_connector, false);
+ if (dret) {
+ radeon_connector->detected_by_load = false;
+ if (radeon_connector->edid) {
+@@ -947,7 +947,7 @@ radeon_dvi_detect(struct drm_connector *
+ return connector->status;
+
+ if (radeon_connector->ddc_bus)
+- dret = radeon_ddc_probe(radeon_connector);
++ dret = radeon_ddc_probe(radeon_connector, false);
+ if (dret) {
+ radeon_connector->detected_by_load = false;
+ if (radeon_connector->edid) {
+@@ -1401,7 +1401,8 @@ radeon_dp_detect(struct drm_connector *c
+ if (encoder) {
+ /* setup ddc on the bridge */
+ radeon_atom_ext_encoder_setup_ddc(encoder);
+- if (radeon_ddc_probe(radeon_connector)) /* try DDC */
++ /* bridge chips are always aux */
++ if (radeon_ddc_probe(radeon_connector, true)) /* try DDC */
+ ret = connector_status_connected;
+ else if (radeon_connector->dac_load_detect) { /* try load detection */
+ struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
+@@ -1419,7 +1420,8 @@ radeon_dp_detect(struct drm_connector *c
+ if (radeon_dp_getdpcd(radeon_connector))
+ ret = connector_status_connected;
+ } else {
+- if (radeon_ddc_probe(radeon_connector))
++ /* try non-aux ddc (DP to DVI/HMDI/etc. adapter) */
++ if (radeon_ddc_probe(radeon_connector, false))
+ ret = connector_status_connected;
+ }
+ }
+--- a/drivers/gpu/drm/radeon/radeon_display.c
++++ b/drivers/gpu/drm/radeon/radeon_display.c
+@@ -695,10 +695,15 @@ int radeon_ddc_get_modes(struct radeon_c
+ if (radeon_connector->router.ddc_valid)
+ radeon_router_select_ddc_port(radeon_connector);
+
+- if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
+- (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) ||
+- (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
+- ENCODER_OBJECT_ID_NONE)) {
++ if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
++ ENCODER_OBJECT_ID_NONE) {
++ struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
++
++ if (dig->dp_i2c_bus)
++ radeon_connector->edid = drm_get_edid(&radeon_connector->base,
++ &dig->dp_i2c_bus->adapter);
++ } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
++ (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
+ struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
+
+ if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
+--- a/drivers/gpu/drm/radeon/radeon_i2c.c
++++ b/drivers/gpu/drm/radeon/radeon_i2c.c
+@@ -39,7 +39,7 @@ extern u32 radeon_atom_hw_i2c_func(struc
+ * radeon_ddc_probe
+ *
+ */
+-bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
++bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux)
+ {
+ u8 out = 0x0;
+ u8 buf[8];
+@@ -63,7 +63,13 @@ bool radeon_ddc_probe(struct radeon_conn
+ if (radeon_connector->router.ddc_valid)
+ radeon_router_select_ddc_port(radeon_connector);
+
+- ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
++ if (use_aux) {
++ struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
++ ret = i2c_transfer(&dig->dp_i2c_bus->adapter, msgs, 2);
++ } else {
++ ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
++ }
++
+ if (ret != 2)
+ /* Couldn't find an accessible DDC on this connector */
+ return false;
+--- a/drivers/gpu/drm/radeon/radeon_mode.h
++++ b/drivers/gpu/drm/radeon/radeon_mode.h
+@@ -559,7 +559,7 @@ extern void radeon_i2c_put_byte(struct r
+ u8 val);
+ extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
+ extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
+-extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
++extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
+ extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
+
+ extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
--- /dev/null
+From d3493574e267c203836bfdcb9c58d8af46fc0da1 Mon Sep 17 00:00:00 2001
+From: Jerome Glisse <jglisse@redhat.com>
+Date: Fri, 14 Dec 2012 16:20:46 -0500
+Subject: drm/radeon: restore modeset late in GPU reset path
+
+From: Jerome Glisse <jglisse@redhat.com>
+
+commit d3493574e267c203836bfdcb9c58d8af46fc0da1 upstream.
+
+Modeset path seems to conflict sometimes with the memory management
+leading to kernel deadlock. This move modesetting reset after GPU
+acceleration reset.
+
+Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_device.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_device.c
++++ b/drivers/gpu/drm/radeon/radeon_device.c
+@@ -1337,7 +1337,6 @@ retry:
+ }
+
+ radeon_restore_bios_scratch_regs(rdev);
+- drm_helper_resume_force_mode(rdev->ddev);
+
+ if (!r) {
+ for (i = 0; i < RADEON_NUM_RINGS; ++i) {
+@@ -1362,6 +1361,8 @@ retry:
+ }
+ }
+
++ drm_helper_resume_force_mode(rdev->ddev);
++
+ ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
+ if (r) {
+ /* bad news, how to tell it to userspace ? */
--- /dev/null
+From ae133a1129790ec288b429b5f08ab4701633844a Mon Sep 17 00:00:00 2001
+From: Christian König <deathsimple@vodafone.de>
+Date: Tue, 18 Sep 2012 15:30:44 -0400
+Subject: drm/radeon: stop page faults from hanging the system (v2)
+
+From: Christian König <deathsimple@vodafone.de>
+
+commit ae133a1129790ec288b429b5f08ab4701633844a upstream.
+
+Redirect invalid memory accesses to the default page
+instead of locking up the memory controller. Also
+enable the invalid memory access interrupts and
+start spamming system log with it.
+
+v2 (agd5f): fix up against 2 level PT changes
+
+Signed-off-by: Christian König <deathsimple@vodafone.de>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/evergreen.c | 10 ++++++++++
+ drivers/gpu/drm/radeon/evergreend.h | 3 +++
+ drivers/gpu/drm/radeon/ni.c | 16 +++++++++++++---
+ drivers/gpu/drm/radeon/nid.h | 11 +++++++++++
+ drivers/gpu/drm/radeon/si.c | 25 +++++++++++++++++++++++--
+ drivers/gpu/drm/radeon/sid.h | 14 ++++++++++++++
+ 6 files changed, 74 insertions(+), 5 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/evergreen.c
++++ b/drivers/gpu/drm/radeon/evergreen.c
+@@ -3093,6 +3093,16 @@ restart_ih:
+ break;
+ }
+ break;
++ case 146:
++ case 147:
++ dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
++ dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
++ RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
++ dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
++ RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
++ /* reset addr and status */
++ WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
++ break;
+ case 176: /* CP_INT in ring buffer */
+ case 177: /* CP_INT in IB1 */
+ case 178: /* CP_INT in IB2 */
+--- a/drivers/gpu/drm/radeon/evergreend.h
++++ b/drivers/gpu/drm/radeon/evergreend.h
+@@ -651,6 +651,7 @@
+ #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
+ #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
+ #define VM_CONTEXT1_CNTL 0x1414
++#define VM_CONTEXT1_CNTL2 0x1434
+ #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
+ #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
+ #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
+@@ -672,6 +673,8 @@
+ #define CACHE_UPDATE_MODE(x) ((x) << 6)
+ #define VM_L2_STATUS 0x140C
+ #define L2_BUSY (1 << 0)
++#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
+
+ #define WAIT_UNTIL 0x8040
+
+--- a/drivers/gpu/drm/radeon/ni.c
++++ b/drivers/gpu/drm/radeon/ni.c
+@@ -784,10 +784,20 @@ static int cayman_pcie_gart_enable(struc
+ /* enable context1-7 */
+ WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
+ (u32)(rdev->dummy_page.addr >> 12));
+- WREG32(VM_CONTEXT1_CNTL2, 0);
+- WREG32(VM_CONTEXT1_CNTL, 0);
++ WREG32(VM_CONTEXT1_CNTL2, 4);
+ WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
+- RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
++ RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
++ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
++ DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
++ DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
++ PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
++ PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
++ VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
++ VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
++ READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
++ READ_PROTECTION_FAULT_ENABLE_DEFAULT |
++ WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
++ WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
+
+ cayman_pcie_gart_tlb_flush(rdev);
+ DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+--- a/drivers/gpu/drm/radeon/nid.h
++++ b/drivers/gpu/drm/radeon/nid.h
+@@ -80,7 +80,18 @@
+ #define VM_CONTEXT0_CNTL 0x1410
+ #define ENABLE_CONTEXT (1 << 0)
+ #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
++#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
+ #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
++#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
++#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
++#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
++#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
++#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
++#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
++#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
++#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
++#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
++#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
+ #define VM_CONTEXT1_CNTL 0x1414
+ #define VM_CONTEXT0_CNTL2 0x1430
+ #define VM_CONTEXT1_CNTL2 0x1434
+--- a/drivers/gpu/drm/radeon/si.c
++++ b/drivers/gpu/drm/radeon/si.c
+@@ -2426,9 +2426,20 @@ static int si_pcie_gart_enable(struct ra
+ /* enable context1-15 */
+ WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
+ (u32)(rdev->dummy_page.addr >> 12));
+- WREG32(VM_CONTEXT1_CNTL2, 0);
++ WREG32(VM_CONTEXT1_CNTL2, 4);
+ WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
+- RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
++ RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
++ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
++ DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
++ DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
++ PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
++ PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
++ VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
++ VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
++ READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
++ READ_PROTECTION_FAULT_ENABLE_DEFAULT |
++ WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
++ WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
+
+ si_pcie_gart_tlb_flush(rdev);
+ DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+@@ -3684,6 +3695,16 @@ restart_ih:
+ break;
+ }
+ break;
++ case 146:
++ case 147:
++ dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
++ dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
++ RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
++ dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
++ RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
++ /* reset addr and status */
++ WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
++ break;
+ case 176: /* RINGID0 CP_INT */
+ radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
+ break;
+--- a/drivers/gpu/drm/radeon/sid.h
++++ b/drivers/gpu/drm/radeon/sid.h
+@@ -91,7 +91,18 @@
+ #define VM_CONTEXT0_CNTL 0x1410
+ #define ENABLE_CONTEXT (1 << 0)
+ #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
++#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
+ #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
++#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
++#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
++#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
++#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
++#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
++#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
++#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
++#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
++#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
++#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
+ #define VM_CONTEXT1_CNTL 0x1414
+ #define VM_CONTEXT0_CNTL2 0x1430
+ #define VM_CONTEXT1_CNTL2 0x1434
+@@ -104,6 +115,9 @@
+ #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
+ #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
+
++#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
++
+ #define VM_INVALIDATE_REQUEST 0x1478
+ #define VM_INVALIDATE_RESPONSE 0x147c
+
--- /dev/null
+From 999a7c5776a0ed2133645fa7e008bec05bda9254 Mon Sep 17 00:00:00 2001
+From: Dan Williams <dcbw@redhat.com>
+Date: Fri, 14 Dec 2012 13:10:50 +0000
+Subject: i2400m: add Intel 6150 device IDs
+
+From: Dan Williams <dcbw@redhat.com>
+
+commit 999a7c5776a0ed2133645fa7e008bec05bda9254 upstream.
+
+Add device IDs for WiMAX function of Intel 6150 cards.
+
+Signed-off-by: Dan Williams <dcbw@redhat.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/net/wimax/i2400m/i2400m-usb.h | 3 +++
+ drivers/net/wimax/i2400m/usb.c | 6 ++++++
+ 2 files changed, 9 insertions(+)
+
+--- a/drivers/net/wimax/i2400m/i2400m-usb.h
++++ b/drivers/net/wimax/i2400m/i2400m-usb.h
+@@ -152,6 +152,9 @@ enum {
+ /* Device IDs */
+ USB_DEVICE_ID_I6050 = 0x0186,
+ USB_DEVICE_ID_I6050_2 = 0x0188,
++ USB_DEVICE_ID_I6150 = 0x07d6,
++ USB_DEVICE_ID_I6150_2 = 0x07d7,
++ USB_DEVICE_ID_I6150_3 = 0x07d9,
+ USB_DEVICE_ID_I6250 = 0x0187,
+ };
+
+--- a/drivers/net/wimax/i2400m/usb.c
++++ b/drivers/net/wimax/i2400m/usb.c
+@@ -510,6 +510,9 @@ int i2400mu_probe(struct usb_interface *
+ switch (id->idProduct) {
+ case USB_DEVICE_ID_I6050:
+ case USB_DEVICE_ID_I6050_2:
++ case USB_DEVICE_ID_I6150:
++ case USB_DEVICE_ID_I6150_2:
++ case USB_DEVICE_ID_I6150_3:
+ case USB_DEVICE_ID_I6250:
+ i2400mu->i6050 = 1;
+ break;
+@@ -759,6 +762,9 @@ static
+ struct usb_device_id i2400mu_id_table[] = {
+ { USB_DEVICE(0x8086, USB_DEVICE_ID_I6050) },
+ { USB_DEVICE(0x8086, USB_DEVICE_ID_I6050_2) },
++ { USB_DEVICE(0x8087, USB_DEVICE_ID_I6150) },
++ { USB_DEVICE(0x8087, USB_DEVICE_ID_I6150_2) },
++ { USB_DEVICE(0x8087, USB_DEVICE_ID_I6150_3) },
+ { USB_DEVICE(0x8086, USB_DEVICE_ID_I6250) },
+ { USB_DEVICE(0x8086, 0x0181) },
+ { USB_DEVICE(0x8086, 0x1403) },
--- /dev/null
+From 6491d4d02893d9787ba67279595990217177b351 Mon Sep 17 00:00:00 2001
+From: "Woodhouse, David" <david.woodhouse@intel.com>
+Date: Wed, 19 Dec 2012 13:25:35 +0000
+Subject: intel-iommu: Free old page tables before creating superpage
+
+From: "Woodhouse, David" <david.woodhouse@intel.com>
+
+commit 6491d4d02893d9787ba67279595990217177b351 upstream.
+
+The dma_pte_free_pagetable() function will only free a page table page
+if it is asked to free the *entire* 2MiB range that it covers. So if a
+page table page was used for one or more small mappings, it's likely to
+end up still present in the page tables... but with no valid PTEs.
+
+This was fine when we'd only be repopulating it with 4KiB PTEs anyway
+but the same virtual address range can end up being reused for a
+*large-page* mapping. And in that case were were trying to insert the
+large page into the second-level page table, and getting a complaint
+from the sanity check in __domain_mapping() because there was already a
+corresponding entry. This was *relatively* harmless; it led to a memory
+leak of the old page table page, but no other ill-effects.
+
+Fix it by calling dma_pte_clear_range (hopefully redundant) and
+dma_pte_free_pagetable() before setting up the new large page.
+
+Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
+Tested-by: Ravi Murty <Ravi.Murty@intel.com>
+Tested-by: Sudeep Dutt <sudeep.dutt@intel.com>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/iommu/intel-iommu.c | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+--- a/drivers/iommu/intel-iommu.c
++++ b/drivers/iommu/intel-iommu.c
+@@ -1827,10 +1827,17 @@ static int __domain_mapping(struct dmar_
+ if (!pte)
+ return -ENOMEM;
+ /* It is large page*/
+- if (largepage_lvl > 1)
++ if (largepage_lvl > 1) {
+ pteval |= DMA_PTE_LARGE_PAGE;
+- else
++ /* Ensure that old small page tables are removed to make room
++ for superpage, if they exist. */
++ dma_pte_clear_range(domain, iov_pfn,
++ iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
++ dma_pte_free_pagetable(domain, iov_pfn,
++ iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
++ } else {
+ pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
++ }
+
+ }
+ /* We don't need lock here, nobody else
--- /dev/null
+From 2cbba75a56ea78e6876b4e2547a882f10b3fe72b Mon Sep 17 00:00:00 2001
+From: Alexey Khoroshilov <khoroshilov@ispras.ru>
+Date: Mon, 5 Nov 2012 22:40:14 +0400
+Subject: jffs2: hold erase_completion_lock on exit
+
+From: Alexey Khoroshilov <khoroshilov@ispras.ru>
+
+commit 2cbba75a56ea78e6876b4e2547a882f10b3fe72b upstream.
+
+Users of jffs2_do_reserve_space() expect they still held
+erase_completion_lock after call to it. But there is a path
+where jffs2_do_reserve_space() leaves erase_completion_lock unlocked.
+The patch fixes it.
+
+Found by Linux Driver Verification project (linuxtesting.org).
+
+Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru>
+Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ fs/jffs2/nodemgmt.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/fs/jffs2/nodemgmt.c
++++ b/fs/jffs2/nodemgmt.c
+@@ -417,14 +417,16 @@ static int jffs2_do_reserve_space(struct
+ spin_unlock(&c->erase_completion_lock);
+
+ ret = jffs2_prealloc_raw_node_refs(c, jeb, 1);
+- if (ret)
+- return ret;
++
+ /* Just lock it again and continue. Nothing much can change because
+ we hold c->alloc_sem anyway. In fact, it's not entirely clear why
+ we hold c->erase_completion_lock in the majority of this function...
+ but that's a question for another (more caffeine-rich) day. */
+ spin_lock(&c->erase_completion_lock);
+
++ if (ret)
++ return ret;
++
+ waste = jeb->free_size;
+ jffs2_link_node_ref(c, jeb,
+ (jeb->offset + c->sector_size - waste) | REF_OBSOLETE,
svcrpc-revert-sunrpc-cache.h-replace-simple_strtoul.patch
sunrpc-ensure-that-we-free-the-rpc_task-after-cleanups-are-done.patch
sunrpc-ensure-we-release-the-socket-write-lock-if-the-rpc_task-exits-early.patch
+jffs2-hold-erase_completion_lock-on-exit.patch
+i2400m-add-intel-6150-device-ids.patch
+intel-iommu-free-old-page-tables-before-creating-superpage.patch
+drm-radeon-stop-page-faults-from-hanging-the-system-v2.patch
+drm-radeon-dce32-use-fractional-fb-dividers-for-high-clocks.patch
+drm-radeon-fix-edp-clk-and-lane-setup-for-scaled-modes.patch
+drm-radeon-fix-amd-afusion-gpu-setup-aka-sumo-v2.patch
+drm-radeon-restore-modeset-late-in-gpu-reset-path.patch
+drm-radeon-don-t-leave-fence-blocked-process-on-failed-gpu-reset.patch
+drm-radeon-avoid-deadlock-in-pm-path-when-waiting-for-fence.patch
+drm-radeon-add-wait_until-to-evergreen-vm-safe-reg-list.patch
+drm-radeon-add-connector-table-for-mac-g4-silver.patch
+drm-radeon-properly-handle-ddc-probe-for-dp-bridges.patch
+drm-nouveau-fix-init-with-agpgart-uninorth.patch
+drm-i915-make-the-panel-fitter-work-on-pipes-b-and-c-on-ivb.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
