drm/amd/display: To support Replay frame skip mode

[Why & How]
The change is to optimize the Replay power saving by
reducing the refresh rate with frame skipping mode

Reviewed-by: Robin Chen <robin.chen@amd.com>
Signed-off-by: Chuntao Tso <chunttso@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
index 80704d709e44a1c0460554826af27ca0c6c78f72..da94e3544b657ff54a252faf3ca9f9df90b5c633 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
@@ -162,7 +162,7 @@ bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool wait)
 
        if (link) {
                link->dc->link_srv->edp_setup_replay(link, stream);
-               link->dc->link_srv->edp_set_coasting_vtotal(link, stream->timing.v_total);
+               link->dc->link_srv->edp_set_coasting_vtotal(link, stream->timing.v_total, 0);
                DRM_DEBUG_DRIVER("Enabling replay...\n");
                link->dc->link_srv->edp_set_replay_allow_active(link, &replay_active, wait, false, NULL);
                return true;

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index ea6b71c43d2c8bb35c8011e269f44531d0a60284..0495e6cfcca0752af21f13ac5d804db9b3acd8dd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -1184,6 +1184,10 @@ struct replay_settings {
        uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM];
        /* Defer Update Coasting vtotal table */
        uint32_t defer_update_coasting_vtotal_table[PR_COASTING_TYPE_NUM];
+       /* Skip frame number table */
+       uint32_t frame_skip_number_table[PR_COASTING_TYPE_NUM];
+       /* Defer skip frame number table */
+       uint32_t defer_frame_skip_number_table[PR_COASTING_TYPE_NUM];
        /* Maximum link off frame count */
        uint32_t link_off_frame_count;
        /* Replay pseudo vtotal for low refresh rate*/
@@ -1192,6 +1196,8 @@ struct replay_settings {
        uint16_t last_pseudo_vtotal;
        /* Replay desync error */
        uint32_t replay_desync_error_fail_count;
+       /* The frame skip number dal send to DMUB */
+       uint16_t frame_skip_number;
 };
 
 /* To split out "global" and "per-panel" config settings.

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
index f9542edff14bb018bc6968459c4e407c890f667c..fd8244c946874c9883bd74d4ab31f189b7cb95a2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
@@ -213,7 +213,8 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub,
  */
 static void dmub_replay_set_coasting_vtotal(struct dmub_replay *dmub,
                uint32_t coasting_vtotal,
-               uint8_t panel_inst)
+               uint8_t panel_inst,
+               uint16_t frame_skip_number)
 {
        union dmub_rb_cmd cmd;
        struct dc_context *dc = dmub->ctx;
@@ -227,6 +228,7 @@ static void dmub_replay_set_coasting_vtotal(struct dmub_replay *dmub,
        pCmd->header.payload_bytes = sizeof(struct dmub_cmd_replay_set_coasting_vtotal_data);
        pCmd->replay_set_coasting_vtotal_data.coasting_vtotal = (coasting_vtotal & 0xFFFF);
        pCmd->replay_set_coasting_vtotal_data.coasting_vtotal_high = (coasting_vtotal & 0xFFFF0000) >> 16;
+       pCmd->replay_set_coasting_vtotal_data.frame_skip_number = frame_skip_number;
 
        dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 }
@@ -283,7 +285,7 @@ static void dmub_replay_residency(struct dmub_replay *dmub, uint8_t panel_inst,
  * Set REPLAY power optimization flags and coasting vtotal.
  */
 static void dmub_replay_set_power_opt_and_coasting_vtotal(struct dmub_replay *dmub,
-               unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal)
+               unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal, uint16_t frame_skip_number)
 {
        union dmub_rb_cmd cmd;
        struct dc_context *dc = dmub->ctx;
@@ -301,6 +303,7 @@ static void dmub_replay_set_power_opt_and_coasting_vtotal(struct dmub_replay *dm
        pCmd->replay_set_power_opt_data.panel_inst = panel_inst;
        pCmd->replay_set_coasting_vtotal_data.coasting_vtotal = (coasting_vtotal & 0xFFFF);
        pCmd->replay_set_coasting_vtotal_data.coasting_vtotal_high = (coasting_vtotal & 0xFFFF0000) >> 16;
+       pCmd->replay_set_coasting_vtotal_data.frame_skip_number = frame_skip_number;
 
        dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
index e6346c0ffc0e444392c09b421404cd3c50284ba7..07c79739a98092794f47976bc6fa6d2001fbeb28 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
@@ -27,11 +27,12 @@ struct dmub_replay_funcs {
        void (*replay_send_cmd)(struct dmub_replay *dmub,
                enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_element);
        void (*replay_set_coasting_vtotal)(struct dmub_replay *dmub, uint32_t coasting_vtotal,
-               uint8_t panel_inst);
+               uint8_t panel_inst, uint16_t frame_skip_number);
        void (*replay_residency)(struct dmub_replay *dmub,
                uint8_t panel_inst, uint32_t *residency, const bool is_start, const enum pr_residency_mode mode);
        void (*replay_set_power_opt_and_coasting_vtotal)(struct dmub_replay *dmub,
-               unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal);
+               unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal,
+               uint16_t frame_skip_number);
 };
 
 struct dmub_replay *dmub_replay_create(struct dc_context *ctx);

diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_service.h b/drivers/gpu/drm/amd/display/dc/inc/link_service.h
index 1e34e84160aa658314fd5b818ab9d5d157823e06..6f94e48a24d1b45bb3400a538dd0d2d25644b831 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/link_service.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_service.h
@@ -292,12 +292,12 @@ struct link_service {
                        enum replay_FW_Message_type msg,
                        union dmub_replay_cmd_set *cmd_data);
        bool (*edp_set_coasting_vtotal)(
-                       struct dc_link *link, uint32_t coasting_vtotal);
+                       struct dc_link *link, uint32_t coasting_vtotal, uint16_t frame_skip_number);
        bool (*edp_replay_residency)(const struct dc_link *link,
                        unsigned int *residency, const bool is_start,
                        const enum pr_residency_mode mode);
        bool (*edp_set_replay_power_opt_and_coasting_vtotal)(struct dc_link *link,
-                       const unsigned int *power_opts, uint32_t coasting_vtotal);
+                       const unsigned int *power_opts, uint32_t coasting_vtotal, uint16_t frame_skip_number);
 
        bool (*edp_wait_for_t12)(struct dc_link *link);
        bool (*edp_is_ilr_optimization_required)(struct dc_link *link,

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index 5e806edbb9f610fd061d2e75a72f779115b8b401..9391c75a30e57a8c1aa2b9219972c3c2ae7b2d74 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -1110,7 +1110,7 @@ bool edp_send_replay_cmd(struct dc_link *link,
        return true;
 }
 
-bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal)
+bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal, uint16_t frame_skip_number)
 {
        struct dc *dc = link->ctx->dc;
        struct dmub_replay *replay = dc->res_pool->replay;
@@ -1122,9 +1122,11 @@ bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal)
        if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
                return false;
 
-       if (coasting_vtotal && link->replay_settings.coasting_vtotal != coasting_vtotal) {
-               replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, panel_inst);
+       if (coasting_vtotal && (link->replay_settings.coasting_vtotal != coasting_vtotal ||
+               link->replay_settings.frame_skip_number != frame_skip_number)) {
+               replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, panel_inst, frame_skip_number);
                link->replay_settings.coasting_vtotal = coasting_vtotal;
+               link->replay_settings.frame_skip_number = frame_skip_number;
        }
 
        return true;
@@ -1152,7 +1154,7 @@ bool edp_replay_residency(const struct dc_link *link,
 }
 
 bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,
-       const unsigned int *power_opts, uint32_t coasting_vtotal)
+       const unsigned int *power_opts, uint32_t coasting_vtotal, uint16_t frame_skip_number)
 {
        struct dc  *dc = link->ctx->dc;
        struct dmub_replay *replay = dc->res_pool->replay;
@@ -1163,13 +1165,16 @@ bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,
 
        /* Only both power and coasting vtotal changed, this func could return true */
        if (power_opts && link->replay_settings.replay_power_opt_active != *power_opts &&
-               coasting_vtotal && link->replay_settings.coasting_vtotal != coasting_vtotal) {
+               (coasting_vtotal &&
+               (link->replay_settings.coasting_vtotal != coasting_vtotal ||
+               link->replay_settings.frame_skip_number != frame_skip_number))) {
                if (link->replay_settings.replay_feature_enabled &&
                        replay->funcs->replay_set_power_opt_and_coasting_vtotal) {
                        replay->funcs->replay_set_power_opt_and_coasting_vtotal(replay,
-                               *power_opts, panel_inst, coasting_vtotal);
+                               *power_opts, panel_inst, coasting_vtotal, frame_skip_number);
                        link->replay_settings.replay_power_opt_active = *power_opts;
                        link->replay_settings.coasting_vtotal = coasting_vtotal;
+                       link->replay_settings.frame_skip_number = frame_skip_number;
                } else
                        return false;
        } else

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
index 62a6344e613e32c7054fbdcafc1b629a9f782af5..dd79c7cd2828df31c3f9c65c5547586dec6c2d86 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
@@ -59,12 +59,12 @@ bool edp_setup_replay(struct dc_link *link,
 bool edp_send_replay_cmd(struct dc_link *link,
                        enum replay_FW_Message_type msg,
                        union dmub_replay_cmd_set *cmd_data);
-bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal);
+bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal, uint16_t frame_skip_number);
 bool edp_replay_residency(const struct dc_link *link,
        unsigned int *residency, const bool is_start, const enum pr_residency_mode mode);
 bool edp_get_replay_state(const struct dc_link *link, uint64_t *state);
 bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,
-       const unsigned int *power_opts, uint32_t coasting_vtotal);
+       const unsigned int *power_opts, uint32_t coasting_vtotal, uint16_t frame_skip_number);
 bool edp_wait_for_t12(struct dc_link *link);
 bool edp_is_ilr_optimization_required(struct dc_link *link,
        struct dc_crtc_timing *crtc_timing);

diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 29ccd3532d139b555b34b0e3481940b2efa91012..88b5b716a0847ad6c01ed6fa7f0b519349c713f7 100644 (file)
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -975,6 +975,34 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,
        return true;
 }
 
+void set_replay_frame_skip_number(struct dc_link *link,
+       enum replay_coasting_vtotal_type type,
+       uint32_t coasting_vtotal_refresh_rate_mhz,
+       uint32_t flicker_free_refresh_rate_mhz,
+       bool is_defer)
+{
+       uint32_t *frame_skip_number_array = NULL;
+       uint32_t frame_skip_number = 0;
+
+       if (link == NULL || flicker_free_refresh_rate_mhz == 0 || coasting_vtotal_refresh_rate_mhz == 0)
+               return;
+
+       if (is_defer)
+               frame_skip_number_array = link->replay_settings.defer_frame_skip_number_table;
+       else
+               frame_skip_number_array = link->replay_settings.frame_skip_number_table;
+
+       if (frame_skip_number_array == NULL)
+               return;
+
+       frame_skip_number = coasting_vtotal_refresh_rate_mhz / flicker_free_refresh_rate_mhz;
+
+       if (frame_skip_number >= 1)
+               frame_skip_number_array[type] = frame_skip_number - 1;
+       else
+               frame_skip_number_array[type] = 0;
+}
+
 void set_replay_defer_update_coasting_vtotal(struct dc_link *link,
        enum replay_coasting_vtotal_type type,
        uint32_t vtotal)
@@ -987,6 +1015,8 @@ void update_replay_coasting_vtotal_from_defer(struct dc_link *link,
 {
        link->replay_settings.coasting_vtotal_table[type] =
                link->replay_settings.defer_update_coasting_vtotal_table[type];
+       link->replay_settings.frame_skip_number_table[type] =
+               link->replay_settings.defer_frame_skip_number_table[type];
 }
 
 void set_replay_coasting_vtotal(struct dc_link *link,

diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
index 391209a3bf29842bafe90be23f335a765b8db113..87d31d9dce5a688a65ac273a692b38b18c1e7161 100644 (file)
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
@@ -60,6 +60,11 @@ void set_replay_coasting_vtotal(struct dc_link *link,
 void set_replay_defer_update_coasting_vtotal(struct dc_link *link,
        enum replay_coasting_vtotal_type type,
        uint32_t vtotal);
+void set_replay_frame_skip_number(struct dc_link *link,
+       enum replay_coasting_vtotal_type type,
+       uint32_t coasting_vtotal_refresh_rate_Mhz,
+       uint32_t flicker_free_refresh_rate_Mhz,
+       bool is_defer);
 void update_replay_coasting_vtotal_from_defer(struct dc_link *link,
        enum replay_coasting_vtotal_type type);
 void set_replay_low_rr_full_screen_video_src_vtotal(struct dc_link *link, uint16_t vtotal);