+2017-06-27 Segher Boessenkool <segher@kernel.crashing.org>
+
+ Backports from trunk:
+
+ 2016-08-15 Segher Boessenkool <segher@kernel.crashing.org>
+ PR rtl-optimization/73650
+ * lra-constraints.c (simple_move_p): If the insn is multiple_sets
+ it is not a simple move.
+
+ 2017-01-20 Segher Boessenkool <segher@kernel.crashing.org>
+ PR target/61729
+ PR target/77850
+ * config/rs6000/rs6000.c (rs6000_gimplify_va_arg): Adjust address to
+ read from, for big endian.
+
+ 2017-04-04 Segher Boessenkool <segher@kernel.crashing.org>
+ PR rtl-optimization/60818
+ * simplify-rtx.c (simplify_binary_operation_1): Do not replace
+ a compare of comparisons with the thing compared if this results
+ in a different machine mode.
+
+ 2017-04-12 Segher Boessenkool <segher@kernel.crashing.org>
+ PR target/80382
+ * config/rs6000/sync.md (atomic_load<mode>, atomic_store<mode): Test
+ for quad_address_p for TImode, instead of just not indexed_address.
+
+ 2017-04-19 Segher Boessenkool <segher@kernel.crashing.org>
+ PR rtl-optimization/80429
+ * ira.c (split_live_ranges_for_shrink_wrap): Don't split regs that
+ are only used in debug insns.
+
+ 2017-05-17 Segher Boessenkool <segher@kernel.crashing.org>
+ PR middle-end/80692
+ * real.c (do_compare): Give decimal_do_compare preference over
+ comparing just the signs.
+
+ 2017-05-31 Segher Boessenkool <segher@kernel.crashing.org>
+ PR target/80618
+ * config/rs6000/vector.md (*vector_uneq<mode>): Write the nor in the
+ splitter result in the canonical way.
+
+ 2017-06-09 Segher Boessenkool <segher@kernel.crashing.org>
+ PR target/80966
+ * config/rs6000/rs6000.c (rs6000_emit_allocate_stack): Assert that
+ gen_add3_insn did not fail.
+ * config/rs6000/rs6000.md (add<mode>3): If asked to add a constant to
+ r0, construct that number in a temporary reg and add that reg to r0.
+ If asked to put the result in r0 as well, fail.
+
+ 2017-06-23 Segher Boessenkool <segher@kernel.crashing.org>
+ PR middle-end/80902
+ * builtins.c (expand_builtin_atomic_fetch_op): If emitting code after
+ a call, force the call to not be a tail call.
+
2017-06-23 Thomas Preud'homme <thomas.preudhomme@arm.com>
Backport from mainline
gcc_assert (TREE_OPERAND (addr, 0) == fndecl);
TREE_OPERAND (addr, 0) = builtin_decl_explicit (ext_call);
+ /* If we will emit code after the call, the call can not be a tail call.
+ If it is emitted as a tail call, a barrier is emitted after it, and
+ then all trailing code is removed. */
+ if (!ignore)
+ CALL_EXPR_TAILCALL (exp) = 0;
+
/* Expand the call here so we can emit trailing code. */
ret = expand_call (exp, target, ignore);
size = int_size_in_bytes (type);
rsize = (size + 3) / 4;
+ int pad = 4 * rsize - size;
align = 1;
machine_mode mode = TYPE_MODE (type);
&& mode == SDmode)
t = fold_build_pointer_plus_hwi (t, size);
+ /* Args are right-aligned. */
+ if (BYTES_BIG_ENDIAN)
+ t = fold_build_pointer_plus_hwi (t, pad);
+
gimplify_assign (addr, t, pre_p);
gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
build_int_cst (TREE_TYPE (t), -align));
}
+
+ /* Args are right-aligned. */
+ if (BYTES_BIG_ENDIAN)
+ t = fold_build_pointer_plus_hwi (t, pad);
+
gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
gimplify_assign (unshare_expr (addr), t, pre_p);
&& REGNO (stack_limit_rtx) > 1
&& REGNO (stack_limit_rtx) <= 31)
{
- emit_insn (gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size)));
- emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
- const0_rtx));
+ rtx_insn *insn
+ = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
+ gcc_assert (insn);
+ emit_insn (insn);
+ emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
}
else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
&& TARGET_32BIT
|| rtx_equal_p (operands[0], operands[1]))
? operands[0] : gen_reg_rtx (<MODE>mode));
+ /* Adding a constant to r0 is not a valid insn, so use a different
+ strategy in that case. */
+ if (REGNO (operands[1]) == 0 || REGNO (tmp) == 0)
+ {
+ if (operands[0] == operands[1])
+ FAIL;
+ rs6000_emit_move (operands[0], operands[2], <MODE>mode);
+ emit_insn (gen_add<mode>3 (operands[0], operands[1], operands[0]));
+ DONE;
+ }
+
HOST_WIDE_INT val = INTVAL (operands[2]);
HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
rtx op1 = operands[1];
rtx pti_reg = gen_reg_rtx (PTImode);
- // Can't have indexed address for 'lq'
- if (indexed_address (XEXP (op1, 0), TImode))
+ if (!quad_address_p (XEXP (op1, 0), TImode, false))
{
rtx old_addr = XEXP (op1, 0);
rtx new_addr = force_reg (Pmode, old_addr);
rtx op1 = operands[1];
rtx pti_reg = gen_reg_rtx (PTImode);
- // Can't have indexed address for 'stq'
- if (indexed_address (XEXP (op0, 0), TImode))
+ if (!quad_address_p (XEXP (op0, 0), TImode, false))
{
rtx old_addr = XEXP (op0, 0);
rtx new_addr = force_reg (Pmode, old_addr);
(gt:VEC_F (match_dup 2)
(match_dup 1)))
(set (match_dup 0)
- (not:VEC_F (ior:VEC_F (match_dup 3)
- (match_dup 4))))]
- "
+ (and:VEC_F (not:VEC_F (match_dup 3))
+ (not:VEC_F (match_dup 4))))]
{
operands[3] = gen_reg_rtx (<MODE>mode);
operands[4] = gen_reg_rtx (<MODE>mode);
-}")
+})
(define_insn_and_split "*vector_ltgt<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
if (!dest || dest == pic_offset_table_rtx)
continue;
- rtx newreg = NULL_RTX;
+ bool need_newreg = false;
df_ref use, next;
for (use = DF_REG_USE_CHAIN (REGNO (dest)); use; use = next)
{
rtx_insn *uin = DF_REF_INSN (use);
next = DF_REF_NEXT_REG (use);
+ if (DEBUG_INSN_P (uin))
+ continue;
+
basic_block ubb = BLOCK_FOR_INSN (uin);
if (ubb == call_dom
|| dominated_by_p (CDI_DOMINATORS, ubb, call_dom))
{
- if (!newreg)
- newreg = ira_create_new_reg (dest);
- validate_change (uin, DF_REF_REAL_LOC (use), newreg, true);
+ need_newreg = true;
+ break;
}
}
- if (newreg)
+ if (need_newreg)
{
+ rtx newreg = ira_create_new_reg (dest);
+
+ for (use = DF_REG_USE_CHAIN (REGNO (dest)); use; use = next)
+ {
+ rtx_insn *uin = DF_REF_INSN (use);
+ next = DF_REF_NEXT_REG (use);
+
+ basic_block ubb = BLOCK_FOR_INSN (uin);
+ if (ubb == call_dom
+ || dominated_by_p (CDI_DOMINATORS, ubb, call_dom))
+ validate_change (uin, DF_REF_REAL_LOC (use), newreg, true);
+ }
+
rtx_insn *new_move = gen_move_insn (newreg, dest);
emit_insn_after (new_move, bb_note (call_dom));
if (dump_file)
lra_assert (curr_insn_set != NULL_RTX);
dest = SET_DEST (curr_insn_set);
src = SET_SRC (curr_insn_set);
+
+ /* If the instruction has multiple sets we need to process it even if it
+ is single_set. This can happen if one or more of the SETs are dead.
+ See PR73650. */
+ if (multiple_sets (curr_insn))
+ return false;
+
return ((dclass = get_op_class (dest)) != NO_REGS
&& (sclass = get_op_class (src)) != NO_REGS
/* The backend guarantees that register moves of cost 2
gcc_unreachable ();
}
- if (a->sign != b->sign)
- return -a->sign - -b->sign;
-
if (a->decimal || b->decimal)
return decimal_do_compare (a, b, nan_result);
+ if (a->sign != b->sign)
+ return -a->sign - -b->sign;
+
if (REAL_EXP (a) > REAL_EXP (b))
ret = 1;
else if (REAL_EXP (a) < REAL_EXP (b))
return xop00;
if (REG_P (xop00) && REG_P (xop10)
- && GET_MODE (xop00) == GET_MODE (xop10)
&& REGNO (xop00) == REGNO (xop10)
- && GET_MODE_CLASS (GET_MODE (xop00)) == MODE_CC
- && GET_MODE_CLASS (GET_MODE (xop10)) == MODE_CC)
+ && GET_MODE (xop00) == mode
+ && GET_MODE (xop10) == mode
+ && GET_MODE_CLASS (mode) == MODE_CC)
return xop00;
}
break;
+2017-06-27 Segher Boessenkool <segher@kernel.crashing.org>
+
+ Backports from trunk:
+
+ 2017-04-04 Segher Boessenkool <segher@kernel.crashing.org>
+ PR rtl-optimization/60818
+ * gcc.c-torture/compile/pr60818.c: New testcase.
+
+ 2017-05-17 Segher Boessenkool <segher@kernel.crashing.org>
+ PR middle-end/80692
+ * gcc.c-torture/execute/pr80692.c: New testcase.
+
+ 2017-06-09 Segher Boessenkool <segher@kernel.crashing.org>
+ PR target/80966
+ * gcc.target/powerpc/stack-limit.c: New testcase.
+
2017-06-24 Marek Polacek <polacek@redhat.com>
Backported from mainline
--- /dev/null
+int
+lx (int oi, int mb)
+{
+ return (oi < mb) < (mb < oi);
+}
--- /dev/null
+/* { dg-require-effective-target dfp } */
+
+int main () {
+ _Decimal64 d64 = -0.DD;
+
+ if (d64 != 0.DD)
+ __builtin_abort ();
+
+ if (d64 != -0.DD)
+ __builtin_abort ();
+
+ return 0;
+}
--- /dev/null
+/* { dg-options "-O0 -fstack-limit-register=r14" } */
+
+// PR80966
+
+int foo (int i)
+{
+ char arr[135000];
+
+ arr[i] = 0;
+}
projects / thirdparty / gcc.git / commitdiff
