vex_state->guest_DFLAG = 1; /* forwards */
vex_state->guest_IDFLAG = 0;
- // HACK
+ /* HACK: represent the offset associated with %fs==0. This
+ assumes that %fs is only ever zero. */
vex_state->guest_FS_ZERO = 0;
vex_state->guest_RIP = 0;
- // XXX: add more here later, for segment registers, FPU, etc.
+ /* Initialise the SSE state. */
+# define SSEZERO(_xmm) _xmm[0]=_xmm[1]=_xmm[2]=_xmm[3] = 0;
+
+ vex_state->guest_SSEROUND = (ULong)Irrm_NEAREST;
+ SSEZERO(vex_state->guest_XMM0);
+ SSEZERO(vex_state->guest_XMM1);
+ SSEZERO(vex_state->guest_XMM2);
+ SSEZERO(vex_state->guest_XMM3);
+ SSEZERO(vex_state->guest_XMM4);
+ SSEZERO(vex_state->guest_XMM5);
+ SSEZERO(vex_state->guest_XMM6);
+ SSEZERO(vex_state->guest_XMM7);
+ SSEZERO(vex_state->guest_XMM8);
+ SSEZERO(vex_state->guest_XMM9);
+ SSEZERO(vex_state->guest_XMM10);
+ SSEZERO(vex_state->guest_XMM11);
+ SSEZERO(vex_state->guest_XMM12);
+ SSEZERO(vex_state->guest_XMM13);
+ SSEZERO(vex_state->guest_XMM14);
+ SSEZERO(vex_state->guest_XMM15);
+
+# undef SSEZERO
vex_state->guest_EMWARN = EmWarn_NONE;
}
/*--- Vex's representation of the AMD64 CPU state. ---*/
/*---------------------------------------------------------------*/
+/* See detailed comments at the top of libvex_guest_x86.h for
+ further info. This representation pretty closely mimics the
+ x86 representation.
+
+ SSEROUND[1:0] is the SSE unit's notional rounding mode, encoded as
+ per the IRRoundingMode type.
+*/
+
+
typedef
struct {
/* 0 */ ULong guest_RAX;
associated with a %fs value of zero. */
ULong guest_FS_ZERO;
+ /* XMM registers */
+ ULong guest_SSEROUND;
+ U128 guest_XMM0;
+ U128 guest_XMM1;
+ U128 guest_XMM2;
+ U128 guest_XMM3;
+ U128 guest_XMM4;
+ U128 guest_XMM5;
+ U128 guest_XMM6;
+ U128 guest_XMM7;
+ U128 guest_XMM8;
+ U128 guest_XMM9;
+ U128 guest_XMM10;
+ U128 guest_XMM11;
+ U128 guest_XMM12;
+ U128 guest_XMM13;
+ U128 guest_XMM14;
+ U128 guest_XMM15;
+
/* Emulation warnings */
UInt guest_EMWARN;
/* Padding to make it have an 8-aligned size */