drm/amdgpu/vcn: Register dump cleanup in VCN5

Use generic vcn devcoredump helper functions for VCN5

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index f9dbd2757d836e0576a8ddd12060491b29cac912..455f829b8bb99515d70aaf7e8ba4cbc36670f5fe 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -115,21 +115,6 @@ static int vcn_v5_0_0_early_init(struct amdgpu_ip_block *ip_block)
        return 0;
 }
 
-void vcn_v5_0_0_alloc_ip_dump(struct amdgpu_device *adev)
-{
-       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
-       uint32_t *ptr;
-
-       /* Allocate memory for VCN IP Dump buffer */
-       ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
-       if (!ptr) {
-               DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
-               adev->vcn.ip_dump = NULL;
-       } else {
-               adev->vcn.ip_dump = ptr;
-       }
-}
-
 /**
  * vcn_v5_0_0_sw_init - sw init for VCN block
  *
@@ -201,7 +186,9 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)
        if (!amdgpu_sriov_vf(adev))
                adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
 
-       vcn_v5_0_0_alloc_ip_dump(adev);
+       r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_5_0, ARRAY_SIZE(vcn_reg_list_5_0));
+       if (r)
+               return r;
 
        r = amdgpu_vcn_sysfs_reset_mask_init(adev);
        if (r)
@@ -251,8 +238,6 @@ static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block)
                        return r;
        }
 
-       kfree(adev->vcn.ip_dump);
-
        return 0;
 }
 
@@ -1434,67 +1419,6 @@ static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev)
        }
 }
 
-void vcn_v5_0_0_print_ip_state(struct amdgpu_ip_block *ip_block,
-                              struct drm_printer *p)
-{
-       struct amdgpu_device *adev = ip_block->adev;
-       int i, j;
-       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
-       uint32_t inst_off, is_powered;
-
-       if (!adev->vcn.ip_dump)
-               return;
-
-       drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
-       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-               if (adev->vcn.harvest_config & (1 << i)) {
-                       drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
-                       continue;
-               }
-
-               inst_off = i * reg_count;
-               is_powered = (adev->vcn.ip_dump[inst_off] &
-                               UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
-
-               if (is_powered) {
-                       drm_printf(p, "\nActive Instance:VCN%d\n", i);
-                       for (j = 0; j < reg_count; j++)
-                               drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_5_0[j].reg_name,
-                                          adev->vcn.ip_dump[inst_off + j]);
-               } else {
-                       drm_printf(p, "\nInactive Instance:VCN%d\n", i);
-               }
-       }
-}
-
-void vcn_v5_0_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
-{
-       struct amdgpu_device *adev = ip_block->adev;
-       int i, j;
-       bool is_powered;
-       uint32_t inst_off;
-       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
-
-       if (!adev->vcn.ip_dump)
-               return;
-
-       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-               if (adev->vcn.harvest_config & (1 << i))
-                       continue;
-
-               inst_off = i * reg_count;
-               /* mmUVD_POWER_STATUS is always readable and is first element of the array */
-               adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
-               is_powered = (adev->vcn.ip_dump[inst_off] &
-                               UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
-
-               if (is_powered)
-                       for (j = 1; j < reg_count; j++)
-                               adev->vcn.ip_dump[inst_off + j] =
-                                       RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], i));
-       }
-}
-
 static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
        .name = "vcn_v5_0_0",
        .early_init = vcn_v5_0_0_early_init,
@@ -1508,8 +1432,8 @@ static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
        .wait_for_idle = vcn_v5_0_0_wait_for_idle,
        .set_clockgating_state = vcn_v5_0_0_set_clockgating_state,
        .set_powergating_state = vcn_set_powergating_state,
-       .dump_ip_state = vcn_v5_0_0_dump_ip_state,
-       .print_ip_state = vcn_v5_0_0_print_ip_state,
+       .dump_ip_state = amdgpu_vcn_dump_ip_state,
+       .print_ip_state = amdgpu_vcn_print_ip_state,
 };
 
 const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = {

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h
index b8927652bc50ca4874053b776bcc5a2e2f6830de..51bbccd4360ffa1f665f99a0481d877cbf615a2e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h
@@ -32,11 +32,6 @@
 #define VCN_VID_IP_ADDRESS                         0x0
 #define VCN_AON_IP_ADDRESS                         0x30000
 
-void vcn_v5_0_0_alloc_ip_dump(struct amdgpu_device *adev);
-void vcn_v5_0_0_print_ip_state(struct amdgpu_ip_block *ip_block,
-                              struct drm_printer *p);
-void vcn_v5_0_0_dump_ip_state(struct amdgpu_ip_block *ip_block);
-
 extern const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block;
 
 #endif /* __VCN_V5_0_0_H__ */

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
index 74f811fed79a2c0b36887a551ac305b8c6100fea..02a0516edabefca11762a846a9efabc10986671a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
@@ -40,6 +40,40 @@
 
 #include <drm/drm_drv.h>
 
+static const struct amdgpu_hwip_reg_entry vcn_reg_list_5_0_1[] = {
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
+       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)
+};
+
 static int vcn_v5_0_1_start_sriov(struct amdgpu_device *adev);
 static void vcn_v5_0_1_set_unified_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev);
@@ -163,7 +197,9 @@ static int vcn_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block)
                        return r;
        }
 
-       vcn_v5_0_0_alloc_ip_dump(adev);
+       r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_5_0_1, ARRAY_SIZE(vcn_reg_list_5_0_1));
+       if (r)
+               return r;
 
        return amdgpu_vcn_sysfs_reset_mask_init(adev);
 }
@@ -209,8 +245,6 @@ static int vcn_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block)
 
        amdgpu_vcn_sysfs_reset_mask_fini(adev);
 
-       kfree(adev->vcn.ip_dump);
-
        return 0;
 }
 
@@ -1480,8 +1514,8 @@ static const struct amd_ip_funcs vcn_v5_0_1_ip_funcs = {
        .post_soft_reset = NULL,
        .set_clockgating_state = vcn_v5_0_1_set_clockgating_state,
        .set_powergating_state = vcn_set_powergating_state,
-       .dump_ip_state = vcn_v5_0_0_dump_ip_state,
-       .print_ip_state = vcn_v5_0_0_print_ip_state,
+       .dump_ip_state = amdgpu_vcn_dump_ip_state,
+       .print_ip_state = amdgpu_vcn_print_ip_state,
 };
 
 const struct amdgpu_ip_block_version vcn_v5_0_1_ip_block = {