]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amd/pm: add smu ras driver framework
authorGangliang Xie <ganglxie@amd.com>
Mon, 15 Sep 2025 04:52:35 +0000 (12:52 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 4 Nov 2025 16:53:58 +0000 (11:53 -0500)
add functions to get smu ras driver

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h

index 3c0b36dd37bf8d7de1723f0fbef4ad1acabba29b..674bcd3c814c0aead71dd30fa0c63867294b575a 100644 (file)
@@ -620,6 +620,7 @@ struct amdgpu_ras {
 
        /* Disable/Enable uniras switch */
        bool uniras_enabled;
+       const struct ras_smu_drv *ras_smu_drv;
 };
 
 struct ras_fs_data {
index 5c4d0eb198c4145fda189a9cf1c9dc4ef922133e..c6f55d3522cd6423341eb02daeed4b4b1044921d 100644 (file)
@@ -2122,3 +2122,10 @@ ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id,
 
        return ret;
 }
+
+const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev)
+{
+       void *pp_handle = adev->powerplay.pp_handle;
+
+       return smu_get_ras_smu_driver(pp_handle);
+}
index c7ea293856827884934f42cd889e048722056500..aa3f427819a097dd0e3c6875ad8cd8ee27203a09 100644 (file)
@@ -612,5 +612,6 @@ int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask);
 bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev);
 bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev,
                                          enum smu_temp_metric_type type);
+const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev);
 
 #endif
index b3510345a32ad5ccada8785a967f2c4b73877b8e..c0e7c45ac0e61afd04f40bb741302faea37dc6fc 100644 (file)
@@ -2803,6 +2803,17 @@ const struct amdgpu_ip_block_version smu_v14_0_ip_block = {
        .funcs = &smu_ip_funcs,
 };
 
+const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle)
+{
+       struct smu_context *smu = (struct smu_context *)handle;
+       const struct ras_smu_drv *tmp = NULL;
+       int ret;
+
+       ret = smu_get_ras_smu_drv(smu, &tmp);
+
+       return ret ? NULL : tmp;
+}
+
 static int smu_load_microcode(void *handle)
 {
        struct smu_context *smu = handle;
index c48028abc8c4466decdc05064624afe86db16ca1..8815fc70b63b02221e373a9dabfd18aee91a8d98 100644 (file)
@@ -1531,6 +1531,12 @@ struct pptable_funcs {
        int (*ras_send_msg)(struct smu_context *smu,
                            enum smu_message_type msg, uint32_t param, uint32_t *read_arg);
 
+
+       /**
+        * @get_ras_smu_drv: Get RAS smu driver interface
+        * Return: ras_smu_drv *
+        */
+       int (*get_ras_smu_drv)(struct smu_context *smu, const struct ras_smu_drv **ras_smu_drv);
 };
 
 typedef enum {
@@ -1795,6 +1801,7 @@ int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type,
                      int level);
 ssize_t smu_get_pm_policy_info(struct smu_context *smu,
                               enum pp_pm_policy p_type, char *sysbuf);
+const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle);
 
 int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg,
                            uint32_t param, uint32_t *readarg);
index de4c944885f6f92ee27045bf871b38a10f5ad232..095f54b7e9e6253cadfdf290e290c202a9c19694 100644 (file)
@@ -3905,6 +3905,26 @@ static void smu_v13_0_6_set_temp_funcs(struct smu_context *smu)
                        == IP_VERSION(13, 0, 12)) ? &smu_v13_0_12_temp_funcs : NULL;
 }
 
+static int smu_v13_0_6_get_ras_smu_drv(struct smu_context *smu, const struct ras_smu_drv **ras_smu_drv)
+{
+       if (!ras_smu_drv)
+               return -EINVAL;
+
+       if (amdgpu_sriov_vf(smu->adev))
+               return -EOPNOTSUPP;
+
+       switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
+       case IP_VERSION(13, 0, 12):
+               *ras_smu_drv = &smu_v13_0_12_ras_smu_drv;
+               break;
+       default:
+               *ras_smu_drv = NULL;
+               break;
+       }
+
+       return 0;
+}
+
 static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
        /* init dpm */
        .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask,
@@ -3964,6 +3984,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
        .dpm_reset_vcn = smu_v13_0_6_reset_vcn,
        .post_init = smu_v13_0_6_post_init,
        .ras_send_msg = smu_v13_0_6_ras_send_msg,
+       .get_ras_smu_drv = smu_v13_0_6_get_ras_smu_drv,
 };
 
 void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)
index c09ecf1a68a0da5b866ae2e46e7de118aed30687..34f6b4b1c3ba0481aebda579f551192038b6fa98 100644 (file)
 #define smu_is_asic_wbrf_supported(smu)                        smu_ppt_funcs(is_asic_wbrf_supported, false, smu)
 #define smu_enable_uclk_shadow(smu, enable)            smu_ppt_funcs(enable_uclk_shadow, 0, smu, enable)
 #define smu_set_wbrf_exclusion_ranges(smu, freq_band_range)            smu_ppt_funcs(set_wbrf_exclusion_ranges, -EOPNOTSUPP, smu, freq_band_range)
+#define smu_get_ras_smu_drv(smu, ras_smu_drv)                  smu_ppt_funcs(get_ras_smu_drv, -EOPNOTSUPP, smu, ras_smu_drv)
 
 #endif
 #endif