]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
gpu: nova-core: program_brom cannot fail
authorTimur Tabi <ttabi@nvidia.com>
Thu, 5 Feb 2026 22:59:22 +0000 (16:59 -0600)
committerAlexandre Courbot <acourbot@nvidia.com>
Tue, 28 Apr 2026 23:13:55 +0000 (08:13 +0900)
Change the signature of the program_brom HAL method to not return
anything.  None of the implementations can actually fail, so they
always return Ok(()).

Signed-off-by: Timur Tabi <ttabi@nvidia.com>
Link: https://patch.msgid.link/20260205225922.2158430-1-ttabi@nvidia.com
[acourbot: fix conflicts when applying.]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drivers/gpu/nova-core/falcon.rs
drivers/gpu/nova-core/falcon/hal.rs
drivers/gpu/nova-core/falcon/hal/ga102.rs
drivers/gpu/nova-core/falcon/hal/tu102.rs

index 33927af4134c1204d1e078a038ea205f6bcc8b79..24cc2c26e28de6ea182f52d9acb20f17efc14069 100644 (file)
@@ -488,7 +488,7 @@ impl<E: FalconEngine + 'static> Falcon<E> {
         }
         self.pio_wr_dmem_slice(bar, fw.dmem_load_params())?;
 
-        self.hal.program_brom(self, bar, &fw.brom_params())?;
+        self.hal.program_brom(self, bar, &fw.brom_params());
 
         bar.write(
             WithBase::of::<E>(),
@@ -647,7 +647,7 @@ impl<E: FalconEngine + 'static> Falcon<E> {
         )?;
         self.dma_wr(bar, &dma_obj, FalconMem::Dmem, fw.dmem_load_params())?;
 
-        self.hal.program_brom(self, bar, &fw.brom_params())?;
+        self.hal.program_brom(self, bar, &fw.brom_params());
 
         // Set `BootVec` to start of non-secure code.
         bar.write(
index a7e5ea8d0272c0345ebbae47dce5ec544566475a..71df33c79884a3cee048c0d9c6ef4c54507e43b7 100644 (file)
@@ -46,7 +46,7 @@ pub(crate) trait FalconHal<E: FalconEngine>: Send + Sync {
     ) -> Result<u32>;
 
     /// Program the boot ROM registers prior to starting a secure firmware.
-    fn program_brom(&self, falcon: &Falcon<E>, bar: &Bar0, params: &FalconBromParams) -> Result;
+    fn program_brom(&self, falcon: &Falcon<E>, bar: &Bar0, params: &FalconBromParams);
 
     /// Check if the RISC-V core is active.
     /// Returns `true` if the RISC-V core is active, `false` otherwise.
index 8368a61ddeef5da2a09cb34879adadef89c7a3c2..3df1ffa159b8a4343b663529058f3186c5be39e5 100644 (file)
@@ -86,7 +86,7 @@ fn signature_reg_fuse_version_ga102(
     Ok(u16::BITS - reg_fuse_version.leading_zeros())
 }
 
-fn program_brom_ga102<E: FalconEngine>(bar: &Bar0, params: &FalconBromParams) -> Result {
+fn program_brom_ga102<E: FalconEngine>(bar: &Bar0, params: &FalconBromParams) {
     bar.write(
         WithBase::of::<E>().at(0),
         regs::NV_PFALCON2_FALCON_BROM_PARAADDR::zeroed().with_value(params.pkc_data_offset),
@@ -104,8 +104,6 @@ fn program_brom_ga102<E: FalconEngine>(bar: &Bar0, params: &FalconBromParams) ->
         WithBase::of::<E>(),
         regs::NV_PFALCON2_FALCON_MOD_SEL::zeroed().with_algo(FalconModSelAlgo::Rsa3k),
     );
-
-    Ok(())
 }
 
 pub(super) struct Ga102<E: FalconEngine>(PhantomData<E>);
@@ -131,8 +129,8 @@ impl<E: FalconEngine> FalconHal<E> for Ga102<E> {
         signature_reg_fuse_version_ga102(&falcon.dev, bar, engine_id_mask, ucode_id)
     }
 
-    fn program_brom(&self, _falcon: &Falcon<E>, bar: &Bar0, params: &FalconBromParams) -> Result {
-        program_brom_ga102::<E>(bar, params)
+    fn program_brom(&self, _falcon: &Falcon<E>, bar: &Bar0, params: &FalconBromParams) {
+        program_brom_ga102::<E>(bar, params);
     }
 
     fn is_riscv_active(&self, bar: &Bar0) -> bool {
index c7a90266cb44572bff7d4bd0bd3ef0dafd9a9deb..d8f5d271811b489cfb195dec9c0765e7fefae387 100644 (file)
@@ -48,9 +48,7 @@ impl<E: FalconEngine> FalconHal<E> for Tu102<E> {
         Ok(0)
     }
 
-    fn program_brom(&self, _falcon: &Falcon<E>, _bar: &Bar0, _params: &FalconBromParams) -> Result {
-        Ok(())
-    }
+    fn program_brom(&self, _falcon: &Falcon<E>, _bar: &Bar0, _params: &FalconBromParams) {}
 
     fn is_riscv_active(&self, bar: &Bar0) -> bool {
         bar.read(regs::NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS::of::<E>())