particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
+config SYS_MALLOC_LEN
+ hex "Define memory for Dynamic allocation"
+ depends on ARCH_ZYNQ
+ help
+ This defines memory to be allocated for Dynamic allocation
+ TODO: Use for other architectures
+
+ config SPL_SYS_MALLOC_F_LEN
+ hex "Size of malloc() pool in SPL before relocation"
+ depends on SYS_MALLOC_F
+ default SYS_MALLOC_F_LEN
+ help
+ Before relocation, memory is very limited on many platforms. Still,
+ we can provide a small malloc() pool if needed. Driver model in
+ particular needs this to operate, so that it can allocate the
+ initial serial device and any others that are needed.
+
+ config TPL_SYS_MALLOC_F_LEN
+ hex "Size of malloc() pool in TPL before relocation"
+ depends on SYS_MALLOC_F
+ default SYS_MALLOC_F_LEN
+ help
+ Before relocation, memory is very limited on many platforms. Still,
+ we can provide a small malloc() pool if needed. Driver model in
+ particular needs this to operate, so that it can allocate the
+ initial serial device and any others that are needed.
+
menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
default y
select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
+ select SPL_BOARD_INIT if SPL
select SPL_OF_CONTROL if SPL
select DM
- select DM_ETH
- select DM_GPIO
select SPL_DM if SPL
- select DM_MMC
select DM_SPI
select DM_SERIAL
select DM_SPI_FLASH
select SPL_SEPARATE_BSS if SPL
select DM_USB if USB
- select BLK
+ select CLK
+ select SPL_CLK
+ select CLK_ZYNQ
+ imply CMD_CLK
+ imply FAT_WRITE
+ imply CMD_SPL
config ARCH_ZYNQMP
- bool "Support Xilinx ZynqMP Platform"
+ bool "Xilinx ZynqMP based platform"
select ARM64
+ select BOARD_LATE_INIT
select DM
select OF_CONTROL
select DM_SERIAL
depends on SPL
default ""
help
- Include PMUFW to boot.bin.
+ Include external PMUFW (Platform Management Unit FirmWare) to
+ a Xilinx bootable image (boot.bin).
+config ZYNQMP_QSPI
+ bool "Configure ZynqMP QSPI"
+ select DM_SPI
+
config ZYNQMP_USB
bool "Configure ZynqMP USB"
armada-xp-gp.dtb \
armada-xp-maxbcm.dtb \
armada-xp-synology-ds414.dtb \
- armada-xp-theadorable.dtb
+ armada-xp-theadorable.dtb \
+ armada-38x-controlcenterdc.dtb
- dtb-$(CONFIG_ARCH_UNIPHIER) += \
- uniphier-ld11-ref.dtb \
- uniphier-ld20-ref.dtb \
- uniphier-ld4-ref.dtb \
- uniphier-ld6b-ref.dtb \
+ dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
+ uniphier-ld11-global.dtb \
+ uniphier-ld11-ref.dtb
+ dtb-$(CONFIG_ARCH_UNIPHIER_LD20) += \
+ uniphier-ld20-global.dtb \
+ uniphier-ld20-ref.dtb
+ dtb-$(CONFIG_ARCH_UNIPHIER_LD4) += \
+ uniphier-ld4-ref.dtb
+ dtb-$(CONFIG_ARCH_UNIPHIER_LD6B) += \
+ uniphier-ld6b-ref.dtb
+ dtb-$(CONFIG_ARCH_UNIPHIER_PRO4) += \
uniphier-pro4-ace.dtb \
uniphier-pro4-ref.dtb \
- uniphier-pro4-sanji.dtb \
- uniphier-pro5-4kbox.dtb \
+ uniphier-pro4-sanji.dtb
+ dtb-$(CONFIG_ARCH_UNIPHIER_PRO5) += \
+ uniphier-pro5-4kbox.dtb
+ dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \
uniphier-pxs2-gentil.dtb \
- uniphier-pxs2-vodka.dtb \
- uniphier-sld3-ref.dtb \
+ uniphier-pxs2-vodka.dtb
+ dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \
+ uniphier-pxs3-ref.dtb
+ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
uniphier-sld8-ref.dtb
- dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
- zynq-zc706.dtb \
- zynq-zed.dtb \
- zynq-zybo.dtb \
- zynq-microzed.dtb \
+
+ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cc108.dtb \
+ zynq-cse-nand.dtb \
+ zynq-cse-nor.dtb \
+ zynq-cse-qspi-parallel.dtb \
zynq-cse-qspi-single.dtb \
+ zynq-cse-qspi-stacked.dtb \
+ zynq-cse-qspi-x1-single.dtb \
+ zynq-cse-qspi-x1-stacked.dtb \
+ zynq-cse-qspi-x2-single.dtb \
+ zynq-cse-qspi-x2-stacked.dtb \
+ zynq-microzed.dtb \
zynq-picozed.dtb \
+ zynq-syzygy-hub.dtb \
zynq-topic-miami.dtb \
+ zynq-topic-miamilite.dtb \
zynq-topic-miamiplus.dtb \
+ zynq-zc702.dtb \
+ zynq-zc706.dtb \
zynq-zc770-xm010.dtb \
zynq-zc770-xm011.dtb \
zynq-zc770-xm012.dtb \
- zynq-zc770-xm013.dtb
+ zynq-zc770-xm013.dtb \
+ zynq-zed.dtb \
+ zynq-zturn-myir.dtb \
+ zynq-zybo.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-ep108.dtb \
+ zynqmp-mini.dtb \
+ zynqmp-mini-qspi-parallel.dtb \
+ zynqmp-mini-qspi-single.dtb \
+ zynqmp-mini-qspi-stacked.dtb \
+ zynqmp-mini-qspi-x1-single.dtb \
+ zynqmp-mini-qspi-x1-stacked.dtb \
+ zynqmp-mini-qspi-x2-single.dtb \
+ zynqmp-mini-qspi-x2-stacked.dtb \
+ zynqmp-mini-nand.dtb \
+ zynqmp-mini-emmc.dtb \
+ zynqmp-zcu100-revA.dtb \
+ zynqmp-zcu100-revB.dtb \
+ zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
zynqmp-zcu102-rev1.0.dtb \
reg = <0xF8000000 0x1000>;
ranges;
clkc: clkc@100 {
+ u-boot,dm-pre-reloc;
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
- fclk-enable = <0>;
+ fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
};
&uart0 {
++ u-boot,dm-pre-reloc;
status = "okay";
};
obj-y += $(init-objs)
endif
- obj-$(CONFIG_ZYNQ_SDHCI) += tap_delays.o
++obj-$(CONFIG_MMC_SDHCI_ZYNQ) += tap_delays.o
+
# Suppress "warning: function declaration isn't a prototype"
CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes
*/
#include <common.h>
- #include <aes.h>
++#include <uboot_aes.h>
#include <sata.h>
#include <ahci.h>
#include <scsi.h>
return 0;
}
- setenv("setup", "setenv baudrate 4800 && setenv bootcmd run veloce");
+ ver = zynqmp_get_silicon_version();
+
+ switch (ver) {
+ case ZYNQMP_CSU_VERSION_VELOCE:
- setenv("setup", "setenv partid auto");
++ env_set("setup", "setenv baudrate 4800 && env_set bootcmd run veloce");
+ case ZYNQMP_CSU_VERSION_EP108:
+ case ZYNQMP_CSU_VERSION_SILICON:
+ case ZYNQMP_CSU_VERSION_QEMU:
- setenv("setup", "setenv partid 0");
++ env_set("setup", "setenv partid auto");
+ break;
+ default:
++ env_set("setup", "setenv partid 0");
+ }
+
ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
if (ret)
return -EINVAL;
return 0;
}
-#ifdef CONFIG_USB_DWC3
-static struct dwc3_device dwc3_device_data0 = {
- .maximum_speed = USB_SPEED_HIGH,
- .base = ZYNQMP_USB0_XHCI_BASEADDR,
- .dr_mode = USB_DR_MODE_PERIPHERAL,
- .index = 0,
-};
+ int checkboard(void)
+ {
+ puts("Board: Xilinx ZynqMP\n");
+ return 0;
+ }
+
+#if defined(CONFIG_AES)
-static struct dwc3_device dwc3_device_data1 = {
- .maximum_speed = USB_SPEED_HIGH,
- .base = ZYNQMP_USB1_XHCI_BASEADDR,
- .dr_mode = USB_DR_MODE_PERIPHERAL,
- .index = 1,
-};
+#define KEY_LEN 64
+#define IV_LEN 24
+#define ZYNQMP_SIP_SVC_PM_SECURE_LOAD 0xC2000019
+#define ZYNQMP_PM_SECURE_AES 0x1
-int usb_gadget_handle_interrupts(int index)
+int aes_decrypt_hw(u8 *key_ptr, u8 *src_ptr, u8 *dst_ptr, u32 len)
{
- dwc3_uboot_handle_interrupt(index);
- return 0;
-}
+ int ret;
+ u32 src_lo, src_hi, wlen;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
-int board_usb_init(int index, enum usb_init_type init)
-{
- debug("%s: index %x\n", __func__, index);
+ if ((ulong)src_ptr != ALIGN((ulong)src_ptr,
+ CONFIG_SYS_CACHELINE_SIZE)) {
+ debug("FAIL: Source address not aligned:%p\n", src_ptr);
+ return -EINVAL;
+ }
-#if defined(CONFIG_USB_GADGET_DOWNLOAD)
- g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
-#endif
+ src_lo = (u32)(ulong)src_ptr;
+ src_hi = upper_32_bits((ulong)src_ptr);
+ wlen = DIV_ROUND_UP(len, 4);
- switch (index) {
- case 0:
- return dwc3_uboot_init(&dwc3_device_data0);
- case 1:
- return dwc3_uboot_init(&dwc3_device_data1);
- };
+ memcpy(src_ptr + len, key_ptr, KEY_LEN + IV_LEN);
+ len = ROUND(len + KEY_LEN + IV_LEN, CONFIG_SYS_CACHELINE_SIZE);
+ flush_dcache_range((ulong)src_ptr, (ulong)(src_ptr + len));
- return -1;
-}
+ ret = invoke_smc(ZYNQMP_SIP_SVC_PM_SECURE_LOAD, src_lo, src_hi, wlen,
+ ZYNQMP_PM_SECURE_AES, ret_payload);
+ if (ret)
+ debug("aes_decrypt_hw fail\n");
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- dwc3_uboot_exit(index);
- return 0;
+ return ret;
}
#endif
-
- int checkboard(void)
- {
- puts("Board: Xilinx ZynqMP\n");
- return 0;
- }
erase - FLASH memory
protect - enable or disable FLASH write protection
- config CMD_ARMFLASH
- #depends on FLASH_CFI_DRIVER
- bool "armflash"
+ config CMD_FPGA
+ bool "fpga"
+ default y
help
- ARM Ltd reference designs flash partition access
+ FPGA support.
+
+ config CMD_FPGA_LOADBP
+ bool "fpga loadbp - load partial bitstream (Xilinx only)"
+ depends on CMD_FPGA
+ help
+ Supports loading an FPGA device from a bitstream buffer containing
+ a partial bitstream.
+
+ config CMD_FPGA_LOADFS
+ bool "fpga loadfs - load bitstream from FAT filesystem (Xilinx only)"
+ depends on CMD_FPGA
+ help
+ Supports loading an FPGA device from a FAT filesystem.
+
+ config CMD_FPGA_LOADMK
+ bool "fpga loadmk - load bitstream from image"
+ depends on CMD_FPGA
+ help
+ Supports loading an FPGA device from a image generated by mkimage.
+
+ config CMD_FPGA_LOADP
+ bool "fpga loadp - load partial bitstream"
+ depends on CMD_FPGA
+ help
+ Supports loading an FPGA device from a bitstream buffer containing
+ a partial bitstream.
+
++config CMD_FPGA_LOAD_SECURE
++ bool "fpga loads"
++ help
++ Enables the fpga loade command which is used to load encrypted
++ bitstreams on to FPGA.
++
+ config CMD_FPGAD
+ bool "fpgad - dump FPGA registers"
+ help
+ (legacy, needs conversion to driver model)
+ Provides a way to dump FPGA registers by calling the board-specific
+ fpga_get_reg() function. This functions similarly to the 'md'
+ command.
+
+ config CMD_FUSE
+ bool "fuse - support for the fuse subssystem"
+ help
+ (deprecated - needs conversion to driver model)
+ This allows reading, sensing, programming or overriding fuses
+ which control the behaviour of the device. The command uses the
+ fuse_...() API.
+
+ config CMD_GPIO
+ bool "gpio"
+ help
+ GPIO support.
+
+ config CMD_GPT
+ bool "GPT (GUID Partition Table) command"
+ select PARTITION_UUIDS
+ select EFI_PARTITION
+ imply RANDOM_UUID
+ help
+ Enable the 'gpt' command to ready and write GPT style partition
+ tables.
+
+ config RANDOM_UUID
+ bool "GPT Random UUID generation"
+ help
+ Enable the generation of partitions with random UUIDs if none
+ are provided.
+
+ config CMD_GPT_RENAME
+ bool "GPT partition renaming commands"
+ depends on CMD_GPT
+ help
+ Enables the 'gpt' command to interchange names on two GPT
+ partitions via the 'gpt swap' command or to rename single
+ partitions via the 'rename' command.
+
+ config CMD_IDE
+ bool "ide - Support for IDE drivers"
+ select IDE
+ help
+ Provides an 'ide' command which allows accessing the IDE drive,
+ reseting the IDE interface, printing the partition table and
+ geting device info. It also enables the 'diskboot' command which
+ permits booting from an IDE drive.
+
+ config CMD_IO
+ bool "io - Support for performing I/O accesses"
+ help
+ Provides an 'iod' command to display I/O space and an 'iow' command
+ to write values to the I/O space. This can be useful for manually
+ checking the state of devices during boot when debugging device
+ drivers, etc.
+
+ config CMD_IOTRACE
+ bool "iotrace - Support for tracing I/O activity"
+ help
+ Provides an 'iotrace' command which supports recording I/O reads and
+ writes in a trace buffer in memory . It also maintains a checksum
+ of the trace records (even if space is exhausted) so that the
+ sequence of I/O accesses can be verified.
+
+ When debugging drivers it is useful to see what I/O accesses were
+ done and in what order.
+
+ Even if the individual accesses are of little interest it can be
+ useful to verify that the access pattern is consistent each time
+ an operation is performed. In this case a checksum can be used to
+ characterise the operation of a driver. The checksum can be compared
+ across different runs of the operation to verify that the driver is
+ working properly.
+
+ In particular, when performing major refactoring of the driver, where
+ the access pattern should not change, the checksum provides assurance
+ that the refactoring work has not broken the driver.
+
+ This works by sneaking into the io.h heder for an architecture and
+ redirecting I/O accesses through iotrace's tracing mechanism.
+
+ For now no commands are provided to examine the trace buffer. The
+ format is fairly simple, so 'md' is a reasonable substitute.
+
+ Note: The checksum feature is only useful for I/O regions where the
+ contents do not change outside of software control. Where this is not
+ suitable you can fall back to manually comparing the addresses. It
+ might be useful to enhance tracing to only checksum the accesses and
+ not the data read/written.
+
+ config CMD_I2C
+ bool "i2c"
+ help
+ I2C support.
+
+ config CMD_LOADB
+ bool "loadb"
+ default y
+ help
+ Load a binary file over serial line.
+
+ config CMD_LOADS
+ bool "loads"
+ default y
+ help
+ Load an S-Record file over serial line
config CMD_MMC
bool "mmc"
static int fpga_get_op(char *opstr);
/* Local defines */
- #define FPGA_NONE -1
- #define FPGA_INFO 0
- #define FPGA_LOAD 1
- #define FPGA_LOADB 2
- #define FPGA_DUMP 3
- #define FPGA_LOADMK 4
- #define FPGA_LOADP 5
- #define FPGA_LOADBP 6
- #define FPGA_LOADFS 7
- #define FPGA_LOADS 8
+ enum {
+ FPGA_NONE = -1,
+ FPGA_INFO,
+ FPGA_LOAD,
+ FPGA_LOADB,
+ FPGA_DUMP,
+ FPGA_LOADMK,
+ FPGA_LOADP,
+ FPGA_LOADBP,
+ FPGA_LOADFS,
++ FPGA_LOADS,
+ };
/* ------------------------------------------------------------------------- */
/* command form:
as early as possible during boot, and this option can enable that
within SPL.
+config SPL_FPGA_LOAD_ARGS_NAME
+ string "FPGA bitstream name"
+ depends on SPL_FPGA_SUPPORT
+ help
+ FPGA image file loaded in MMC/SD boot mode.
+
+config SPL_FPGA_LOAD_ADDR
+ hex "FPGA bitstream loading adddress"
+ depends on SPL_FPGA_LOAD_ARGS_NAME
+ default 0x1000000
+ help
+ Loading address for FPGA image in memory. On Xilinx Zynq this address
+ should be above 1M to make sure that devcfg can dma from this area.
+
config SPL_GPIO_SUPPORT
bool "Support GPIO"
- depends on SPL
help
Enable support for GPIOs (General-purpose Input/Output) in SPL.
GPIOs allow U-Boot to read the state of an input line (high or
err = spl_parse_image_header(spl_image, header);
if (err)
return err;
- err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
+ err = spi_flash_read(flash, payload_offs,
spl_image->size,
- (void *)spl_image->load_addr);
+ (void *)
+ (uintptr_t)spl_image->load_addr);
}
}
--- /dev/null
+ CONFIG_ARM=y
+ CONFIG_SYS_VENDOR="opalkelly"
+ CONFIG_SYS_CONFIG_NAME="syzygy_hub"
+ CONFIG_ARCH_ZYNQ=y
+ CONFIG_SYS_TEXT_BASE=0x4000000
+ CONFIG_SPL_STACK_R_ADDR=0x200000
+ CONFIG_DEFAULT_DEVICE_TREE="zynq-syzygy-hub"
+ CONFIG_DEBUG_UART=y
+ CONFIG_FIT=y
+ CONFIG_FIT_SIGNATURE=y
+ CONFIG_FIT_VERBOSE=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ CONFIG_SPL=y
+ CONFIG_SPL_STACK_R=y
+ CONFIG_SPL_OS_BOOT=y
+ CONFIG_HUSH_PARSER=y
+ CONFIG_SYS_PROMPT="Zynq> "
+ CONFIG_CMD_BOOTZ=y
+ CONFIG_CMD_EEPROM=y
+ # CONFIG_CMD_FLASH is not set
+ CONFIG_CMD_FPGA_LOADBP=y
+ CONFIG_CMD_FPGA_LOADFS=y
+ CONFIG_CMD_FPGA_LOADMK=y
+ CONFIG_CMD_FPGA_LOADP=y
+ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_I2C=y
+ CONFIG_CMD_MMC=y
+ CONFIG_CMD_USB=y
+ # CONFIG_CMD_SETEXPR is not set
+ CONFIG_CMD_TFTPPUT=y
+ CONFIG_CMD_DHCP=y
+ CONFIG_CMD_MII=y
+ CONFIG_CMD_PING=y
+ CONFIG_CMD_CACHE=y
+ CONFIG_CMD_EXT2=y
+ CONFIG_CMD_EXT4=y
+ CONFIG_CMD_EXT4_WRITE=y
+ CONFIG_CMD_FAT=y
+ CONFIG_CMD_FS_GENERIC=y
+ CONFIG_OF_EMBED=y
+ CONFIG_SPL_DM_SEQ_ALIAS=y
+ CONFIG_FPGA_XILINX=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_MMC=y
+ CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
++CONFIG_DM_ETH=y
+ CONFIG_ZYNQ_GEM=y
+ CONFIG_DEBUG_UART_ZYNQ=y
+ CONFIG_DEBUG_UART_BASE=0xe0000000
+ CONFIG_DEBUG_UART_CLOCK=50000000
+ CONFIG_ZYNQ_SERIAL=y
+ CONFIG_USB=y
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_ULPI_VIEWPORT=y
+ CONFIG_USB_ULPI=y
+ CONFIG_USB_STORAGE=y
+ CONFIG_USB_GADGET=y
+ CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+ CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+ CONFIG_CI_UDC=y
+ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_ZYNQ_SDHCI=y
+ CONFIG_DFU_RAM=y
+ CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
--- /dev/null
+ CONFIG_ARM=y
+ CONFIG_SYS_VENDOR="topic"
+ CONFIG_SYS_CONFIG_NAME="topic_miami"
+ CONFIG_ARCH_ZYNQ=y
+ CONFIG_SYS_TEXT_BASE=0x4000000
+ CONFIG_SPL_STACK_R_ADDR=0x200000
+ CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt"
+ CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite"
+ CONFIG_DEBUG_UART=y
+ CONFIG_BOOTDELAY=0
+ # CONFIG_DISPLAY_CPUINFO is not set
+ CONFIG_SPL=y
+ CONFIG_SPL_STACK_R=y
+ CONFIG_HUSH_PARSER=y
+ CONFIG_SYS_PROMPT="zynq-uboot> "
+ CONFIG_CMD_THOR_DOWNLOAD=y
+ CONFIG_CMD_DFU=y
+ # CONFIG_CMD_FLASH is not set
+ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_I2C=y
+ CONFIG_CMD_MMC=y
+ CONFIG_CMD_SF=y
+ CONFIG_CMD_USB=y
+ # CONFIG_CMD_SETEXPR is not set
+ # CONFIG_CMD_NET is not set
+ # CONFIG_CMD_NFS is not set
+ CONFIG_CMD_CACHE=y
+ CONFIG_CMD_EXT4=y
+ CONFIG_CMD_FAT=y
+ CONFIG_CMD_FS_GENERIC=y
+ CONFIG_OF_EMBED=y
+ CONFIG_SPL_DM_SEQ_ALIAS=y
+ CONFIG_DFU_RAM=y
+ CONFIG_FPGA_XILINX=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_MMC=y
+ CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
+ CONFIG_SPI_FLASH=y
+ CONFIG_SPI_FLASH_BAR=y
+ CONFIG_SF_DUAL_FLASH=y
+ CONFIG_SPI_FLASH_STMICRO=y
+ # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+ CONFIG_DEBUG_UART_ZYNQ=y
+ CONFIG_DEBUG_UART_BASE=0xe0000000
+ CONFIG_DEBUG_UART_CLOCK=100000000
+ CONFIG_ZYNQ_SERIAL=y
+ CONFIG_ZYNQ_QSPI=y
+ CONFIG_USB=y
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_ULPI_VIEWPORT=y
+ CONFIG_USB_ULPI=y
+ CONFIG_USB_STORAGE=y
+ CONFIG_USB_GADGET=y
+ CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+ CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
+ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+ CONFIG_CI_UDC=y
+ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_ZYNQ_SDHCI=y
+ CONFIG_DFU_RAM=y
+ CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+ CONFIG_SF_DUAL_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_ETH=y
# CONFIG_NETDEVICES is not set
- CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
CONFIG_ARCH_ZYNQMP=y
+ CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
++CONFIG_IDENT_STRING=" Xilinx ZynqMP EP108"
+CONFIG_ZYNQMP_QSPI=y
CONFIG_ZYNQMP_USB=y
- CONFIG_IDENT_STRING=" Xilinx ZynqMP EP108"
- CONFIG_SYS_TEXT_BASE=0x8000000
++CONFIG_SPI_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
+ CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
- CONFIG_CMD_NAND=y
+ CONFIG_CMD_NAND_LOCK_UNLOCK=y
+CONFIG_CMD_SF=y
- CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
- CONFIG_CMD_DFU=y
- # CONFIG_CMD_FPGA is not set
- CONFIG_CMD_GPIO=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
- CONFIG_ZYNQ_SDHCI=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
+ CONFIG_NAND=y
CONFIG_NAND_ARASAN=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
- CONFIG_USB_GADGET_DOWNLOAD=y
- CONFIG_G_DNL_MANUFACTURER="Xilinx"
- CONFIG_G_DNL_VENDOR_NUM=0x03fd
- CONFIG_G_DNL_PRODUCT_NUM=0x0300
+ CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+ CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
+ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
# CONFIG_REGEX is not set
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
- # CONFIG_MMC is not set
- CONFIG_SYS_TEXT_BASE=0xFFFC0000
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini"
+CONFIG_ARCH_ZYNQMP=y
++CONFIG_SYS_TEXT_BASE=0xFFFC0000
+CONFIG_SYS_MEM_RSVD_FOR_MMU=y
+CONFIG_DEFINE_TCM_OCM_MMAP=y
+CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
- # CONFIG_CMD_IMLS is not set
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini"
+CONFIG_SYS_EXTRA_OPTIONS="MINI_QSPI"
+CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
- # CONFIG_CMD_LOADB is not set
- # CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_DM is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
++# CONFIG_CMD_LOADB is not set
++# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
++# CONFIG_PARTITIONS is not set
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
++# CONFIG_MMC is not set
+# CONFIG_EFI_LOADER is not set
--- /dev/null
- # CONFIG_CMD_IMLS is not set
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="MINI_EMMC"
+CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
- # CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
++# CONFIG_CMD_FLASH is not set
++# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
- # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_MMC=y
- CONFIG_ZYNQ_SDHCI=y
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+# CONFIG_EFI_LOADER is not set
--- /dev/null
- # CONFIG_CMD_IMLS is not set
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="MINI_NAND"
+CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
- # CONFIG_CMD_LOADB is not set
- # CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
- CONFIG_CMD_NAND=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
++# CONFIG_CMD_LOADB is not set
++# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
++# CONFIG_PARTITIONS is not set
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
++# CONFIG_MMC is not set
++CONFIG_NAND=y
+CONFIG_NAND_ARASAN=y
+# CONFIG_EFI_LOADER is not set
--- /dev/null
- # CONFIG_MMC is not set
- CONFIG_SYS_TEXT_BASE=0xFFFC0000
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini"
+CONFIG_ARCH_ZYNQMP=y
++CONFIG_SYS_TEXT_BASE=0xFFFC0000
+CONFIG_SYS_MEM_RSVD_FOR_MMU=y
+CONFIG_ZYNQMP_QSPI=y
+CONFIG_DEFINE_TCM_OCM_MMAP=y
- # CONFIG_CMD_IMLS is not set
++CONFIG_SPI_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi-single"
+CONFIG_SYS_EXTRA_OPTIONS="MINI_QSPI"
+CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
- # CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
++# CONFIG_CMD_FLASH is not set
++# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
- # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
++# CONFIG_PARTITIONS is not set
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
++# CONFIG_MMC is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_EFI_LOADER is not set
--- /dev/null
- # CONFIG_SPL_FAT_SUPPORT is not set
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
++CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
- # CONFIG_SPL_MMC_SUPPORT is not set
- CONFIG_ZYNQMP_QSPI=y
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
- CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1232 revA"
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
++# CONFIG_SPL_FAT_SUPPORT is not set
++CONFIG_ZYNQMP_QSPI=y
++CONFIG_SPI_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1232-revA"
++CONFIG_DEBUG_UART=y
++CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
- CONFIG_HUSH_PARSER=y
+CONFIG_SPL_OS_BOOT=y
- # CONFIG_CMD_IMLS is not set
++CONFIG_SPL_RAM_SUPPORT=y
++CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="ZynqMP> "
- CONFIG_CMD_SF=y
- CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_MEMTEST=y
++CONFIG_CMD_CLK=y
+# CONFIG_CMD_FLASH is not set
- CONFIG_DEBUG_UART=y
+CONFIG_CMD_FPGA_LOADBP=y
++CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
++CONFIG_CMD_SF=y
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_SPL_DM=y
++# CONFIG_BLK is not set
+CONFIG_CLK_ZYNQMP=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_MISC=y
++CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
++CONFIG_ZYNQ_SERIAL=y
+CONFIG_REGEX=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
- # CONFIG_SPL_FAT_SUPPORT is not set
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
++CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
- # CONFIG_SPL_MMC_SUPPORT is not set
- CONFIG_ZYNQMP_QSPI=y
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
- CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1254 revA"
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
++# CONFIG_SPL_FAT_SUPPORT is not set
++CONFIG_ZYNQMP_QSPI=y
++CONFIG_SPI_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1254-revA"
++CONFIG_DEBUG_UART=y
++CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
- CONFIG_HUSH_PARSER=y
+CONFIG_SPL_OS_BOOT=y
- # CONFIG_CMD_IMLS is not set
++CONFIG_SPL_RAM_SUPPORT=y
++CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="ZynqMP> "
- CONFIG_CMD_SF=y
- CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_MEMTEST=y
++CONFIG_CMD_CLK=y
+# CONFIG_CMD_FLASH is not set
- CONFIG_DEBUG_UART=y
+CONFIG_CMD_FPGA_LOADBP=y
++CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
++CONFIG_CMD_SF=y
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_SPL_DM=y
++# CONFIG_BLK is not set
+CONFIG_CLK_ZYNQMP=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_MISC=y
++CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
++CONFIG_ZYNQ_SERIAL=y
+CONFIG_REGEX=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
- # CONFIG_SPL_FAT_SUPPORT is not set
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
++CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
- # CONFIG_SPL_MMC_SUPPORT is not set
- CONFIG_ZYNQMP_QSPI=y
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
- CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1275 revA"
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
++# CONFIG_SPL_FAT_SUPPORT is not set
++CONFIG_ZYNQMP_QSPI=y
++CONFIG_SPI_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA"
++CONFIG_DEBUG_UART=y
++CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
- CONFIG_HUSH_PARSER=y
+CONFIG_SPL_OS_BOOT=y
- # CONFIG_CMD_IMLS is not set
++CONFIG_SPL_RAM_SUPPORT=y
++CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="ZynqMP> "
- CONFIG_CMD_SF=y
- CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_MEMTEST=y
++CONFIG_CMD_CLK=y
+# CONFIG_CMD_FLASH is not set
- CONFIG_DEBUG_UART=y
+CONFIG_CMD_FPGA_LOADBP=y
++CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
++CONFIG_CMD_SF=y
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_SPL_DM=y
++# CONFIG_BLK is not set
+CONFIG_CLK_ZYNQMP=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_MISC=y
++CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
++CONFIG_ZYNQ_SERIAL=y
+CONFIG_REGEX=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
CONFIG_ARCH_ZYNQMP=y
+ CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+ CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
+CONFIG_ZYNQMP_QSPI=y
CONFIG_ZYNQMP_USB=y
- CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
- CONFIG_SYS_TEXT_BASE=0x8000000
++CONFIG_SPI_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
+ CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
+ CONFIG_SPL_RAM_SUPPORT=y
+ CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
- # CONFIG_CMD_IMLS is not set
+ CONFIG_FASTBOOT=y
+ CONFIG_FASTBOOT_FLASH=y
+ CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+ CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
- # CONFIG_CMD_FLASH is not set
- CONFIG_CMD_MMC=y
- CONFIG_CMD_SF=y
- CONFIG_CMD_I2C=y
- CONFIG_CMD_USB=y
+ CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
- CONFIG_CMD_FPGA_LOADP=y
+ # CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
+ CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
+ CONFIG_CMD_GPT=y
+ CONFIG_CMD_I2C=y
+ CONFIG_CMD_MMC=y
++CONFIG_CMD_SF=y
+ CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
- CONFIG_CMD_AES=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
++CONFIG_CMD_AES=y
CONFIG_CMD_EXT4_WRITE=y
+ # CONFIG_SPL_ISO_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
+ CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
- CONFIG_ZYNQ_SDHCI=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2"
CONFIG_ARCH_ZYNQMP=y
+ CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
- # CONFIG_SPL_FAT_SUPPORT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
- # CONFIG_SPL_MMC_SUPPORT is not set
- CONFIG_ZYNQMP_USB=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm016 dc2"
- # CONFIG_MMC is not set
- CONFIG_SYS_TEXT_BASE=0x8000000
+ # CONFIG_SPL_FAT_SUPPORT is not set
+ CONFIG_ZYNQMP_USB=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
+ CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
+ CONFIG_SPL_RAM_SUPPORT=y
+ CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
- # CONFIG_CMD_IMLS is not set
+ CONFIG_FASTBOOT=y
+ CONFIG_FASTBOOT_FLASH=y
+ CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
- # CONFIG_CMD_FLASH is not set
- CONFIG_CMD_NAND=y
- CONFIG_CMD_I2C=y
- CONFIG_CMD_USB=y
+ CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
- CONFIG_CMD_FPGA_LOADP=y
+ # CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
+ CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
+ CONFIG_CMD_GPT=y
+ CONFIG_CMD_I2C=y
+ CONFIG_CMD_NAND_LOCK_UNLOCK=y
+ CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
- CONFIG_CMD_AES=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
++CONFIG_CMD_AES=y
CONFIG_CMD_EXT4_WRITE=y
+ # CONFIG_SPL_ISO_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
--- /dev/null
- CONFIG_ZYNQMP_USB=y
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm017_dc3"
+CONFIG_ARCH_ZYNQMP=y
++CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
- CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm017 dc3"
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
++CONFIG_ZYNQMP_USB=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm017-dc3"
++CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
- # CONFIG_CMD_IMLS is not set
+CONFIG_SPL_OS_BOOT=y
++CONFIG_SPL_RAM_SUPPORT=y
++CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="ZynqMP> "
- # CONFIG_CMD_FLASH is not set
- CONFIG_CMD_MMC=y
- CONFIG_CMD_NAND=y
- CONFIG_CMD_I2C=y
- CONFIG_CMD_USB=y
+CONFIG_CMD_MEMTEST=y
- CONFIG_CMD_FPGA_LOADP=y
++CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
- CONFIG_CMD_AES=y
++# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
++CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_I2C=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
- CONFIG_DM_SCSI=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
++CONFIG_CMD_AES=y
+CONFIG_CMD_EXT4_WRITE=y
++# CONFIG_SPL_ISO_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_ZYNQ_SDHCI=y
++CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
- CONFIG_DEBUG_UART=y
+CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_ZYNQ=y
++CONFIG_NAND=y
+CONFIG_NAND_ARASAN=y
+CONFIG_DM_ETH=y
++CONFIG_PHY_GIGE=y
+CONFIG_ZYNQ_GEM=y
- CONFIG_G_DNL_MANUFACTURER="Xilinx"
- CONFIG_G_DNL_VENDOR_NUM=0x03FD
- CONFIG_G_DNL_PRODUCT_NUM=0x0300
- CONFIG_AES=y
++CONFIG_SCSI=y
++CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
++CONFIG_ZYNQ_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQMP=y
+ CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
- CONFIG_ZYNQMP_QSPI=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm018 dc4"
- CONFIG_SYS_TEXT_BASE=0x8000000
++CONFIG_ZYNQMP_QSPI=y
++CONFIG_SPI_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
+ CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
+ CONFIG_SPL_RAM_SUPPORT=y
+ CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
- # CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
+ CONFIG_CMD_CLK=y
# CONFIG_CMD_FLASH is not set
- CONFIG_CMD_MMC=y
- CONFIG_CMD_SF=y
- CONFIG_CMD_I2C=y
- CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_FPGA_LOADBP=y
+ CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+ CONFIG_CMD_I2C=y
+ CONFIG_CMD_MMC=y
++CONFIG_CMD_SF=y
CONFIG_CMD_TFTPPUT=y
- CONFIG_CMD_AES=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
++CONFIG_CMD_AES=y
CONFIG_CMD_EXT4_WRITE=y
+ # CONFIG_SPL_ISO_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
+ CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
+ CONFIG_MISC=y
CONFIG_DM_MMC=y
- CONFIG_ZYNQ_SDHCI=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
+ CONFIG_SPL_RAM_SUPPORT=y
+ CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
- # CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
+ CONFIG_CMD_CLK=y
# CONFIG_CMD_FLASH is not set
- CONFIG_CMD_MMC=y
- CONFIG_CMD_I2C=y
- CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_FPGA_LOADBP=y
+ CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+ CONFIG_CMD_I2C=y
+ CONFIG_CMD_MMC=y
CONFIG_CMD_TFTPPUT=y
- CONFIG_CMD_AES=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
++CONFIG_CMD_AES=y
CONFIG_CMD_EXT4_WRITE=y
+ # CONFIG_SPL_ISO_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
+ CONFIG_ENV_IS_IN_FAT=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
--- /dev/null
- CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU100 RevA"
- CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100"
+CONFIG_ARCH_ZYNQMP=y
++CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
++CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU100 RevA"
+CONFIG_BOOT_INIT_FILE="board/xilinx/zynqmp/zynqmp-zcu100-revA/regs.txt"
+CONFIG_ZYNQMP_QSPI=y
+CONFIG_ZYNQMP_USB=y
++CONFIG_SPI_GENERIC=y
+CONFIG_ZYNQ_I2C0=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revA"
++CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
- # CONFIG_CMD_IMLS is not set
+CONFIG_SPL_OS_BOOT=y
++CONFIG_SPL_RAM_SUPPORT=y
++CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="ZynqMP> "
- CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
++CONFIG_CMD_CLK=y
++CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
++CONFIG_CMD_FPGA_LOADBP=y
++CONFIG_CMD_FPGA_LOADP=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
- CONFIG_CMD_DFU=y
- CONFIG_CMD_FPGA_LOADP=y
- CONFIG_CMD_FPGA_LOADBP=y
- CONFIG_CMD_GPIO=y
+CONFIG_CMD_USB=y
- CONFIG_CMD_AES=y
+CONFIG_CMD_TFTPPUT=y
- CONFIG_ZYNQ_SDHCI=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
++CONFIG_CMD_AES=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
- CONFIG_DEBUG_UART=y
+CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
- CONFIG_G_DNL_MANUFACTURER="Xilinx"
- CONFIG_G_DNL_VENDOR_NUM=0x03FD
- CONFIG_G_DNL_PRODUCT_NUM=0x0300
- CONFIG_AES=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
++CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
- CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU100 RevB"
- CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100"
+CONFIG_ARCH_ZYNQMP=y
++CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
++CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU100 RevB"
+CONFIG_ZYNQMP_USB=y
+CONFIG_ZYNQ_I2C1=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revB"
++CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
- # CONFIG_CMD_IMLS is not set
+CONFIG_SPL_OS_BOOT=y
++CONFIG_SPL_RAM_SUPPORT=y
++CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="ZynqMP> "
- CONFIG_CMD_I2C=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_MEMTEST=y
++CONFIG_CMD_CLK=y
++CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
++CONFIG_CMD_FPGA_LOADBP=y
++CONFIG_CMD_FPGA_LOADP=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
- CONFIG_CMD_DFU=y
- CONFIG_CMD_FPGA_LOADP=y
- CONFIG_CMD_FPGA_LOADBP=y
- CONFIG_CMD_GPIO=y
+CONFIG_CMD_USB=y
- CONFIG_CMD_AES=y
+CONFIG_CMD_TFTPPUT=y
- CONFIG_ZYNQ_SDHCI=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
++CONFIG_CMD_AES=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
- CONFIG_DEBUG_UART=y
+CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
- CONFIG_G_DNL_MANUFACTURER="Xilinx"
- CONFIG_G_DNL_VENDOR_NUM=0x03FD
- CONFIG_G_DNL_PRODUCT_NUM=0x0300
- CONFIG_AES=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
++CONFIG_ZYNQ_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_ZYNQ_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
- CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU100 RevC"
- CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100"
+CONFIG_ARCH_ZYNQMP=y
++CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
++CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU100 RevC"
+CONFIG_ZYNQMP_USB=y
+CONFIG_ZYNQ_I2C1=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC"
++CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
- # CONFIG_CMD_IMLS is not set
+CONFIG_SPL_OS_BOOT=y
++CONFIG_SPL_RAM_SUPPORT=y
++CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_BOOTMENU=y
- CONFIG_CMD_I2C=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_MEMTEST=y
++CONFIG_CMD_CLK=y
++CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
++CONFIG_CMD_FPGA_LOADBP=y
++CONFIG_CMD_FPGA_LOADP=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
- CONFIG_CMD_DFU=y
- CONFIG_CMD_FPGA_LOADP=y
- CONFIG_CMD_FPGA_LOADBP=y
- CONFIG_CMD_GPIO=y
+CONFIG_CMD_USB=y
- CONFIG_CMD_AES=y
+CONFIG_CMD_TFTPPUT=y
- CONFIG_ZYNQ_SDHCI=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
++CONFIG_CMD_AES=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
- CONFIG_DEBUG_UART=y
+CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
- CONFIG_G_DNL_MANUFACTURER="Xilinx"
- CONFIG_G_DNL_VENDOR_NUM=0x03FD
- CONFIG_G_DNL_PRODUCT_NUM=0x0300
- CONFIG_AES=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
++CONFIG_ZYNQ_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_ZYNQ_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
CONFIG_ARCH_ZYNQMP=y
+ CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+ CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 rev1.0"
+CONFIG_ZYNQMP_QSPI=y
CONFIG_ZYNQMP_USB=y
- CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 rev1.0"
- CONFIG_SYS_TEXT_BASE=0x8000000
++CONFIG_SPI_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0"
+ CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
+ CONFIG_SPL_RAM_SUPPORT=y
+ CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
- # CONFIG_CMD_IMLS is not set
+ CONFIG_FASTBOOT=y
+ CONFIG_FASTBOOT_FLASH=y
+ CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+ CONFIG_CMD_THOR_DOWNLOAD=y
+ CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
- # CONFIG_CMD_FLASH is not set
- CONFIG_CMD_MMC=y
- CONFIG_CMD_SF=y
- CONFIG_CMD_I2C=y
- CONFIG_CMD_USB=y
+ CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
- CONFIG_CMD_FPGA_LOADP=y
+ # CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
+ CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
+ CONFIG_CMD_GPT=y
+ CONFIG_CMD_I2C=y
+ CONFIG_CMD_MMC=y
++CONFIG_CMD_SF=y
+ CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
- CONFIG_CMD_AES=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
++CONFIG_CMD_AES=y
CONFIG_CMD_EXT4_WRITE=y
+ # CONFIG_SPL_ISO_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
+ CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_DM_SCSI=y
+ CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
+ CONFIG_CMD_PCA953X=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
- CONFIG_ZYNQ_SDHCI=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
CONFIG_ARCH_ZYNQMP=y
+ CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+ CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revA"
+CONFIG_ZYNQMP_QSPI=y
CONFIG_ZYNQMP_USB=y
- CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102"
- CONFIG_SYS_TEXT_BASE=0x8000000
++CONFIG_SPI_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA"
+ CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
+ CONFIG_SPL_RAM_SUPPORT=y
+ CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
- # CONFIG_CMD_IMLS is not set
+ CONFIG_FASTBOOT=y
+ CONFIG_FASTBOOT_FLASH=y
+ CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+ CONFIG_CMD_THOR_DOWNLOAD=y
+ CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
- # CONFIG_CMD_FLASH is not set
- CONFIG_CMD_MMC=y
- CONFIG_CMD_SF=y
- CONFIG_CMD_I2C=y
- CONFIG_CMD_USB=y
+ CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
- CONFIG_CMD_FPGA_LOADP=y
+ # CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
+ CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
+ CONFIG_CMD_GPT=y
+ CONFIG_CMD_I2C=y
+ CONFIG_CMD_MMC=y
++CONFIG_CMD_SF=y
+ CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
- CONFIG_CMD_AES=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
++CONFIG_CMD_AES=y
CONFIG_CMD_EXT4_WRITE=y
+ # CONFIG_SPL_ISO_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
+ CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_DM_SCSI=y
+ CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
+ CONFIG_CMD_PCA953X=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
- CONFIG_ZYNQ_SDHCI=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
CONFIG_ARCH_ZYNQMP=y
+ CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+ CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revB"
+CONFIG_ZYNQMP_QSPI=y
CONFIG_ZYNQMP_USB=y
- CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revB"
- CONFIG_SYS_TEXT_BASE=0x8000000
++CONFIG_SPI_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
+ CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
+ CONFIG_SPL_RAM_SUPPORT=y
+ CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
- # CONFIG_CMD_IMLS is not set
+ CONFIG_FASTBOOT=y
+ CONFIG_FASTBOOT_FLASH=y
+ CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+ CONFIG_CMD_THOR_DOWNLOAD=y
+ CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
- # CONFIG_CMD_FLASH is not set
- CONFIG_CMD_MMC=y
- CONFIG_CMD_SF=y
- CONFIG_CMD_I2C=y
- CONFIG_CMD_USB=y
+ CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
- CONFIG_CMD_FPGA_LOADP=y
+ # CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
+ CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
+ CONFIG_CMD_GPT=y
+ CONFIG_CMD_I2C=y
+ CONFIG_CMD_MMC=y
++CONFIG_CMD_SF=y
+ CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
- CONFIG_CMD_AES=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
++CONFIG_CMD_AES=y
CONFIG_CMD_EXT4_WRITE=y
+ # CONFIG_SPL_ISO_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
+ CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_DM_SCSI=y
+ CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
+ CONFIG_CMD_PCA953X=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
- CONFIG_ZYNQ_SDHCI=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
--- /dev/null
- CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU104 revA"
- CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu104"
+CONFIG_ARCH_ZYNQMP=y
++CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
++CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU104 revA"
+CONFIG_ZYNQMP_QSPI=y
+CONFIG_ZYNQMP_USB=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
++CONFIG_SPI_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu104-revA"
++CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
- # CONFIG_CMD_IMLS is not set
+CONFIG_SPL_OS_BOOT=y
++CONFIG_SPL_RAM_SUPPORT=y
++CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="ZynqMP> "
- # CONFIG_CMD_FLASH is not set
- CONFIG_CMD_MMC=y
- CONFIG_CMD_SF=y
- CONFIG_CMD_I2C=y
- CONFIG_CMD_USB=y
++CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMTEST=y
- CONFIG_CMD_FPGA_LOADP=y
++CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
- CONFIG_CMD_AES=y
++# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
++CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_I2C=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_SF=y
++CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
- CONFIG_DM_SCSI=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
++CONFIG_CMD_AES=y
+CONFIG_CMD_EXT4_WRITE=y
++# CONFIG_SPL_ISO_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
++CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_ZYNQ_SDHCI=y
++CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
++CONFIG_CMD_PCA953X=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
- CONFIG_DEBUG_UART=y
+CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_ETH=y
++CONFIG_PHY_GIGE=y
+CONFIG_ZYNQ_GEM=y
- CONFIG_G_DNL_MANUFACTURER="Xilinx"
- CONFIG_G_DNL_VENDOR_NUM=0x03FD
- CONFIG_G_DNL_PRODUCT_NUM=0x0300
- CONFIG_AES=y
++CONFIG_SCSI=y
++CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
++CONFIG_ZYNQ_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
- CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU106 revA"
- CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu106"
+CONFIG_ARCH_ZYNQMP=y
++CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
++CONFIG_SPL_SPI_FLASH_SUPPORT=y
++CONFIG_SPL_SPI_SUPPORT=y
++CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU106 revA"
+CONFIG_ZYNQMP_QSPI=y
+CONFIG_ZYNQMP_USB=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
++CONFIG_SPI_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu106-revA"
++CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
++# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
- # CONFIG_CMD_IMLS is not set
+CONFIG_SPL_OS_BOOT=y
++CONFIG_SPL_RAM_SUPPORT=y
++CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="ZynqMP> "
- # CONFIG_CMD_FLASH is not set
- CONFIG_CMD_MMC=y
- CONFIG_CMD_SF=y
- CONFIG_CMD_I2C=y
- CONFIG_CMD_USB=y
++CONFIG_FASTBOOT=y
++CONFIG_FASTBOOT_FLASH=y
++CONFIG_FASTBOOT_FLASH_MMC_DEV=0
++CONFIG_CMD_THOR_DOWNLOAD=y
++CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMTEST=y
- CONFIG_CMD_FPGA_LOADP=y
++CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
- CONFIG_CMD_AES=y
++# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
++CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_I2C=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_SF=y
++CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
- CONFIG_DM_SCSI=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
++CONFIG_CMD_AES=y
+CONFIG_CMD_EXT4_WRITE=y
++# CONFIG_SPL_ISO_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
++CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_ZYNQ_SDHCI=y
++CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
++CONFIG_CMD_PCA953X=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
- CONFIG_DEBUG_UART=y
+CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_ETH=y
++CONFIG_PHY_GIGE=y
+CONFIG_ZYNQ_GEM=y
- CONFIG_USB_GADGET_DOWNLOAD=y
- CONFIG_G_DNL_MANUFACTURER="Xilinx"
- CONFIG_G_DNL_VENDOR_NUM=0x03FD
- CONFIG_G_DNL_PRODUCT_NUM=0x0300
- CONFIG_AES=y
++CONFIG_SCSI=y
++CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
++CONFIG_ZYNQ_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
++CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
++CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_ZYNQ_SDHCI=y
+ CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
- CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
- CONFIG_DEBUG_UART_BASE=0xe0001000
+ CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_DEBUG_UART_ANNOUNCE=y
+ CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
--- /dev/null
- CONFIG_SYS_MALLOC_LEN=0x20000
- # CONFIG_MMC is not set
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_ARCH_ZYNQ=y
- CONFIG_SYS_NO_FLASH=y
+CONFIG_SYS_TEXT_BASE=0x100000
++CONFIG_SPL_STACK_R_ADDR=0x200000
++CONFIG_SYS_MALLOC_LEN=0x20000
+CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand"
- # CONFIG_CMD_IMLS is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
++CONFIG_SPL_STACK_R=y
+CONFIG_SYS_PROMPT="Zynq> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
- # CONFIG_CMD_LOADB is not set
- # CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_XIMG is not set
++# CONFIG_CMD_SPL is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
++# CONFIG_CMD_CLK is not set
+# CONFIG_CMD_DM is not set
- CONFIG_CMD_NAND=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
++# CONFIG_CMD_LOADB is not set
++# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
++# CONFIG_PARTITIONS is not set
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_SPL_DM_SEQ_ALIAS=y
++# CONFIG_MMC is not set
++CONFIG_NAND=y
+CONFIG_NAND_ZYNQ=y
+# CONFIG_EFI_LOADER is not set
--- /dev/null
- # CONFIG_MMC is not set
- CONFIG_SYS_TEXT_BASE=0xFFFC0000
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_ARCH_ZYNQ=y
++CONFIG_SYS_TEXT_BASE=0xFFFC0000
++CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_SYS_MALLOC_LEN=0x1000
+CONFIG_ZYNQ_M29EW_WB_HACK=y
- # CONFIG_CMD_IMLS is not set
+CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor"
+CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
++CONFIG_SPL_STACK_R=y
+CONFIG_SYS_PROMPT="Zynq> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
- # CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_XIMG is not set
++# CONFIG_CMD_SPL is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
++# CONFIG_CMD_CLK is not set
+# CONFIG_CMD_DM is not set
++# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
++# CONFIG_PARTITIONS is not set
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_SPL_DM_SEQ_ALIAS=y
++# CONFIG_MMC is not set
+# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
CONFIG_ARCH_ZYNQ=y
- CONFIG_SYS_MALLOC_LEN=0x1000
- # CONFIG_MMC is not set
CONFIG_SYS_TEXT_BASE=0xFFFC0000
+ CONFIG_SPL_STACK_R_ADDR=0x200000
+ # CONFIG_ZYNQ_DDRC_INIT is not set
++CONFIG_SYS_MALLOC_LEN=0x1000
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
+ CONFIG_DEBUG_UART=y
+ # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=-1
- CONFIG_SYS_NO_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+ CONFIG_SPL_STACK_R=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
-# CONFIG_SPL_BLK is not set
-# CONFIG_ZYNQ_GPIO is not set
+ # CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
- CONFIG_ZYNQ_SDHCI=y
+ CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
+ CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
- CONFIG_ZYNQ_SDHCI=y
+ CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
+ CONFIG_ZYNQ_SERIAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
--- /dev/null
+ CONFIG_ARM=y
+ CONFIG_ARCH_ZYNQ=y
+ CONFIG_SYS_TEXT_BASE=0x4000000
+ CONFIG_SPL_STACK_R_ADDR=0x200000
+ CONFIG_DEFAULT_DEVICE_TREE="zynq-zturn-myir"
+ CONFIG_DEBUG_UART=y
+ CONFIG_FIT=y
+ CONFIG_FIT_SIGNATURE=y
+ CONFIG_FIT_VERBOSE=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ CONFIG_SPL=y
+ CONFIG_SPL_STACK_R=y
+ CONFIG_SPL_OS_BOOT=y
+ CONFIG_HUSH_PARSER=y
+ CONFIG_SYS_PROMPT="Zynq> "
+ CONFIG_CMD_THOR_DOWNLOAD=y
+ CONFIG_CMD_DFU=y
+ # CONFIG_CMD_FLASH is not set
+ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_MMC=y
+ CONFIG_CMD_SF=y
+ CONFIG_CMD_USB=y
+ # CONFIG_CMD_SETEXPR is not set
+ CONFIG_CMD_TFTPPUT=y
+ CONFIG_CMD_DHCP=y
+ CONFIG_CMD_MII=y
+ CONFIG_CMD_PING=y
+ CONFIG_CMD_CACHE=y
+ CONFIG_CMD_EXT2=y
+ CONFIG_CMD_EXT4=y
+ CONFIG_CMD_EXT4_WRITE=y
+ CONFIG_CMD_FAT=y
+ CONFIG_CMD_FS_GENERIC=y
+ CONFIG_NET_RANDOM_ETHADDR=y
+ CONFIG_SPL_DM_SEQ_ALIAS=y
+ CONFIG_DFU_MMC=y
+ CONFIG_DFU_RAM=y
+ CONFIG_FPGA_XILINX=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_MMC=y
+ CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
+ CONFIG_SPI_FLASH=y
+ CONFIG_SPI_FLASH_BAR=y
+ CONFIG_SPI_FLASH_SPANSION=y
+ CONFIG_SPI_FLASH_STMICRO=y
+ CONFIG_SPI_FLASH_WINBOND=y
++CONFIG_DM_ETH=y
+ CONFIG_ZYNQ_GEM=y
+ CONFIG_DEBUG_UART_ZYNQ=y
+ CONFIG_DEBUG_UART_BASE=0xe0001000
+ CONFIG_DEBUG_UART_CLOCK=50000000
+ CONFIG_ZYNQ_SERIAL=y
+ CONFIG_ZYNQ_QSPI=y
+ CONFIG_USB=y
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_ULPI_VIEWPORT=y
+ CONFIG_USB_ULPI=y
+ CONFIG_USB_STORAGE=y
+ CONFIG_USB_GADGET=y
+ CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+ CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+ CONFIG_CI_UDC=y
+ CONFIG_USB_GADGET_DOWNLOAD=y
--- /dev/null
- CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
+CONFIG_ARCH_ZYNQ=y
++CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_IDENT_STRING=" Xilinx Zynq ZC702"
- CONFIG_FIT_VERBOSE=y
++CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
++CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
- CONFIG_SYS_NO_FLASH=y
+CONFIG_FIT_SIGNATURE=y
- # CONFIG_CMD_IMLS is not set
++CONFIG_FIT_VERBOSE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
++CONFIG_SPL_STACK_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
- CONFIG_CMD_I2C=y
++CONFIG_CMD_THOR_DOWNLOAD=y
++CONFIG_CMD_EEPROM=y
++CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
++CONFIG_CMD_FPGA_LOADBP=y
++CONFIG_CMD_FPGA_LOADFS=y
++CONFIG_CMD_FPGA_LOADMK=y
++CONFIG_CMD_FPGA_LOADP=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
- CONFIG_CMD_DFU=y
- CONFIG_CMD_GPIO=y
+CONFIG_CMD_USB=y
- CONFIG_ZYNQ_SDHCI=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_ZYNQ_AES=y
+CONFIG_CMD_ZYNQ_RSA=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
++CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
++CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
- CONFIG_DEBUG_UART=y
+CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_ZYNQ_GEM=y
- CONFIG_G_DNL_MANUFACTURER="Xilinx"
- CONFIG_G_DNL_VENDOR_NUM=0x03fd
- CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
++CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
++CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
++CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
- CONFIG_SYS_TEXT_BASE=0x4000000
+ CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_IDENT_STRING=" Xilinx Zynq ZC702"
+ CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
+ CONFIG_DEBUG_UART=y
CONFIG_FIT=y
- CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
- CONFIG_SYS_NO_FLASH=y
+ CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+ CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
- CONFIG_ZYNQ_SDHCI=y
+ CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
- CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
- CONFIG_IDENT_STRING=" Xilinx Zynq ZC706"
CONFIG_SYS_TEXT_BASE=0x4000000
++CONFIG_IDENT_STRING=" Xilinx Zynq ZC706"
+ CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
+ CONFIG_DEBUG_UART=y
CONFIG_FIT=y
- CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
- CONFIG_SYS_NO_FLASH=y
+ CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+ CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
- CONFIG_ZYNQ_SDHCI=y
+ CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
- CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
- CONFIG_SYS_TEXT_BASE=0x4000000
+ CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM010"
+ CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
+ CONFIG_DEBUG_UART=y
CONFIG_FIT=y
- CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
+ CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
- CONFIG_SYS_NO_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+ CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_ZYNQ_SDHCI=y
+ CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
- CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
- CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011"
- # CONFIG_MMC is not set
CONFIG_SYS_TEXT_BASE=0x4000000
++CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011"
+ CONFIG_SPL_STACK_R_ADDR=0x200000
+ # CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011"
++CONFIG_DEBUG_UART=y
CONFIG_FIT=y
- CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
+ CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
- CONFIG_SYS_NO_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+ CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+ CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
+ # CONFIG_MMC is not set
+CONFIG_DM_MMC=y
+ CONFIG_NAND=y
CONFIG_NAND_ZYNQ=y
+CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
- CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+ CONFIG_ZYNQ_SERIAL=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
- CONFIG_ZYNQ_M29EW_WB_HACK=y
- CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM012"
- # CONFIG_MMC is not set
CONFIG_SYS_TEXT_BASE=0x4000000
++CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM012"
+ CONFIG_SPL_STACK_R_ADDR=0x200000
+ # CONFIG_SPL_FAT_SUPPORT is not set
++CONFIG_ZYNQ_M29EW_WB_HACK=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
CONFIG_FIT=y
- CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
+ CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_DM_MMC=y
+ CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
+ # CONFIG_MMC is not set
+ CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
+ CONFIG_ZYNQ_SERIAL=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
- CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM013"
- # CONFIG_MMC is not set
CONFIG_SYS_TEXT_BASE=0x4000000
++CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM013"
+ CONFIG_SPL_STACK_R_ADDR=0x200000
+ # CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
CONFIG_FIT=y
- CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
+ CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
- CONFIG_SYS_NO_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+ CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_DM_MMC=y
+ CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
+ # CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
+ CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
- CONFIG_ZYNQ_SDHCI=y
+ CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
++CONFIG_SF_DUAL_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
+ CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
- CONFIG_ZYNQ_SDHCI=y
+ CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
- CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
return dm_mmc_get_cd(mmc->dev);
}
- #endif
+int dm_mmc_set_voltage(struct udevice *dev)
+{
+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+ if (!ops->set_voltage)
+ return -ENOSYS;
+
+ return ops->set_voltage(dev);
+}
+
+int mmc_set_voltage(struct mmc *mmc)
+{
+ return dm_mmc_set_voltage(mmc->dev);
+}
+
+int dm_mmc_set_uhs(struct udevice *dev)
+{
+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+ if (!ops->set_uhs)
+ return -ENOSYS;
+
+ return ops->set_uhs(dev);
+}
+
+int mmc_switch_uhs(struct mmc *mmc)
+{
+ return dm_mmc_set_uhs(mmc->dev);
+}
+
+int dm_mmc_execute_tuning(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
+ u8 opcode;
+
+ if (!ops->execute_tuning)
+ return -ENOSYS;
+
+ if (IS_SD(mmc))
+ opcode = MMC_CMD_SEND_TUNING_BLOCK;
+ else
+ opcode = MMC_CMD_SEND_TUNING_BLOCK_HS200;
+
+ return ops->execute_tuning(dev, opcode);
+}
+
+int mmc_execute_tuning(struct mmc *mmc)
+{
+ return dm_mmc_execute_tuning(mmc->dev);
+}
+
struct mmc *mmc_get_mmc_dev(struct udevice *dev)
{
struct mmc_uclass_priv *upriv;
return 0;
}
- #ifndef CONFIG_DM_MMC_OPS
++#ifndef CONFIG_DM_MMC
+static int mmc_set_voltage(struct mmc *mmc)
+{
+ int err = 0;
+
+ if (mmc->cfg->ops->set_voltage) {
+ err = mmc->cfg->ops->set_voltage(mmc);
+ if (err)
+ return err;
+ }
+
+ return err;
+}
+#endif
+
+static int mmc_switch_voltage(struct mmc *mmc)
+{
+ struct mmc_cmd cmd;
+ int err = 0;
+
+ cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_NONE;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ return err;
+
+ err = mmc_set_voltage(mmc);
+
+ return err;
+}
+
+static int mmc_host_uhs(struct mmc *mmc)
+{
+ return mmc->cfg->host_caps &
+ (MMC_MODE_UHS_SDR12 | MMC_MODE_UHS_SDR25 |
+ MMC_MODE_UHS_SDR50 | MMC_MODE_UHS_SDR104 |
+ MMC_MODE_UHS_DDR50);
+}
+
static int sd_send_op_cond(struct mmc *mmc)
{
int timeout = 1000;
}
- #ifndef CONFIG_DM_MMC_OPS
++#ifndef CONFIG_DM_MMC
+static void mmc_set_ios(struct mmc *mmc)
+{
+ if (mmc->cfg->ops->set_ios)
+ mmc->cfg->ops->set_ios(mmc);
+}
+#endif
+
+static void mmc_set_bus_width(struct mmc *mmc, uint width)
+{
+ mmc->bus_width = width;
+
+ mmc_set_ios(mmc);
+}
+
+static int mmc_select_bus_width(struct mmc *mmc)
+{
+ /* Only version 4 of MMC supports wider bus widths */
+ int idx;
+ int err;
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
+
+
+ /* An array of possible bus widths in order of preference */
+ static unsigned ext_csd_bits[] = {
+ EXT_CSD_BUS_WIDTH_8,
+ EXT_CSD_BUS_WIDTH_4,
+ };
+
+ /* An array to map CSD bus widths to host cap bits */
+ static unsigned ext_to_hostcaps[] = {
+ [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
+ [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
+ };
+
+ /* An array to map chosen bus width to an integer */
+ static unsigned widths[] = {
+ 8, 4,
+ };
+
+ err = mmc_send_ext_csd(mmc, ext_csd);
+
+ for (idx = 0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
+ unsigned int extw = ext_csd_bits[idx];
+ unsigned int caps = ext_to_hostcaps[extw];
+
+ /*
+ * If the bus width is still not changed,
+ * don't try to set the default again.
+ * Otherwise, recover from switch attempts
+ * by switching to 1-bit bus width.
+ */
+ if (extw == EXT_CSD_BUS_WIDTH_1 &&
+ mmc->bus_width == 1) {
+ err = 0;
+ break;
+ }
+
+ /*
+ * Check to make sure the card and controller support
+ * these capabilities
+ */
+ if ((mmc->card_caps & caps) != caps)
+ continue;
+
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_BUS_WIDTH, extw);
+
+ if (err)
+ continue;
+
+ mmc_set_bus_width(mmc, widths[idx]);
+
+ err = mmc_send_ext_csd(mmc, test_csd);
+ if (err)
+ continue;
+
+ /* Only compare read only fields */
+ if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
+ == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
+ ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
+ == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
+ ext_csd[EXT_CSD_REV]
+ == test_csd[EXT_CSD_REV] &&
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
+ == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
+ memcmp(&ext_csd[EXT_CSD_SEC_CNT],
+ &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
+ break;
+ else
+ err = -EBADMSG;
+ }
+
+ if (err)
+ return err;
+
+ return 0;
+}
+
static int mmc_change_freq(struct mmc *mmc)
{
ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
mmc_set_ios(mmc);
}
- #ifndef CONFIG_DM_MMC_OPS
-static void mmc_set_bus_width(struct mmc *mmc, uint width)
++#ifndef CONFIG_DM_MMC
+static int mmc_switch_uhs(struct mmc *mmc)
{
- mmc->bus_width = width;
+ int err = 0;
- mmc_set_ios(mmc);
+ if (mmc->cfg->ops->set_uhs)
+ err = mmc->cfg->ops->set_uhs(mmc);
+
+ return err;
}
+static int mmc_execute_tuning(struct mmc *mmc)
+{
+ int err = 0;
+ u8 cmd;
+
+ if (mmc->cfg->ops->execute_tuning) {
+ if (IS_SD(mmc))
+ cmd = MMC_CMD_SEND_TUNING_BLOCK;
+ else
+ cmd = MMC_CMD_SEND_TUNING_BLOCK_HS200;
+ err = mmc->cfg->ops->execute_tuning(mmc, cmd);
+ }
+
+ return err;
+}
+#endif
+
static int mmc_startup(struct mmc *mmc)
{
int err, i;
else
return -ECOMM;
}
- #ifdef CONFIG_DM_MMC_OPS
++#ifdef CONFIG_DM_MMC
+static int sdhci_execute_tuning(struct udevice *dev, u8 opcode)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static int sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+#endif
+ struct mmc_cmd cmd;
+ struct mmc_data data;
+ u32 ctrl;
+ int err;
+ u8 tuning_loop_counter = 40;
+ struct sdhci_host *host = mmc->priv;
+
+ debug("%s\n", __func__);
+
+ if (host->platform_execute_tuning) {
+ err = host->platform_execute_tuning(mmc, opcode);
+ if (err)
+ return err;
+ return 0;
+ }
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
+ ctrl |= SDHCI_CTRL_EXEC_TUNING;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
+
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
+
+ do {
+ cmd.cmdidx = opcode;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = 0;
+
+ data.blocksize = 64;
+ data.blocks = 1;
+ data.flags = MMC_DATA_READ;
+
+ if (tuning_loop_counter == 0)
+ break;
+
+ tuning_loop_counter--;
+
+ if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
+ mmc->bus_width == 8) {
+ data.blocksize = 128;
+ }
+
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
+ data.blocksize),
+ SDHCI_BLOCK_SIZE);
+ sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
+ sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
+
+ sdhci_send_command(dev, &cmd, &data);
+ ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
+
+ if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+ udelay(1);
+
+ } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
+
+ if (tuning_loop_counter < 0) {
+ ctrl &= ~SDHCI_CTRL_TUNED_CLK;
+ sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
+ }
+
+ if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
+ debug("%s:Tuning failed\n", __func__);
+ return -1;
+ }
+
+ /* Enable only interrupts served by the SD controller */
+ sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
+ SDHCI_INT_ENABLE);
+ /* Mask all sdhci interrupt sources */
+ sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
+
+ return 0;
+}
static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
return 0;
}
- #ifdef CONFIG_DM_MMC_OPS
++#ifdef CONFIG_DM_MMC
+static int sdhci_set_voltage(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static int sdhci_set_voltage(struct mmc *mmc)
+{
+#endif
+ struct sdhci_host *host = mmc->priv;
+ u32 reg;
+ int err;
+
+ debug("%s\n", __func__);
+
+ reg = (unsigned long)host->ioaddr + SDHCI_PRESENT_STATE;
+ /* Wait max 20ms for the bits to clear*/
+ err = wait_for_bit(__func__, (const u32 *)(uintptr_t)reg,
+ (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT),
+ false, 20, false);
+ if (err < 0)
+ return err;
+
+ reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
+ sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
+
+ /* keep clock gated for 5 msec as per spec */
+ udelay(5000);
+
+ reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
+ reg |= SDHCI_18V_SIGNAL;
+ sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
+
+ sdhci_set_clock(mmc, mmc->cfg->f_min);
+
+ reg = (unsigned long)host->ioaddr + SDHCI_PRESENT_STATE;
+ /* Wait max 20ms for bits to be clear */
+ err = wait_for_bit(__func__, (const u32 *)(uintptr_t)reg,
+ (SDHCI_CMD_BUSY | SDHCI_DATA_BUSY),
+ true, 20, false);
+ if (err < 0)
+ return err;
+
+ return 0;
+}
+
- #ifdef CONFIG_DM_MMC_OPS
++#ifdef CONFIG_DM_MMC
+static int sdhci_set_uhs(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static int sdhci_set_uhs(struct mmc *mmc)
+{
+#endif
+ struct sdhci_host *host = mmc->priv;
+ u32 reg;
+
+ debug("%s\n", __func__);
+ reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
+ reg &= ~SDHCI_CTRL2_MODE_MASK;
+ reg |= mmc->uhsmode;
+ sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
+
+ return 0;
+}
+
static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
{
u8 pwr = 0;
#endif
int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
- u32 max_clk, u32 min_clk)
+ u32 f_max, u32 f_min)
{
- u32 caps, caps_1;
+ u32 caps;
+ u32 caps_1 = 0;
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
cfg->voltages |= host->voltages;
cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
+
+ /* Since Host Controller Version3.0 */
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
- if (caps & SDHCI_CAN_DO_8BIT)
- cfg->host_caps |= MMC_MODE_8BIT;
+ if (!(caps & SDHCI_CAN_DO_8BIT))
+ cfg->host_caps &= ~MMC_MODE_8BIT;
}
- /*
- * In case of Host Controller v3.00, find out whether clock
- * multiplier is supported.
- */
- if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
- caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
- host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
- SDHCI_CLOCK_MUL_SHIFT;
+ if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
+ caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+
+ if (!(cfg->voltages & MMC_VDD_165_195) ||
+ (host->quirks & SDHCI_QUIRK_NO_1_8_V))
+ caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
+ SDHCI_SUPPORT_DDR50);
+
+ if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
+ SDHCI_SUPPORT_DDR50))
+ cfg->host_caps |= MMC_MODE_UHS_SDR12 | MMC_MODE_UHS_SDR25;
+
+ if (caps_1 & SDHCI_SUPPORT_SDR104) {
+ cfg->host_caps |= MMC_MODE_UHS_SDR104 | MMC_MODE_UHS_SDR50;
+ /*
+ * SD3.0: SDR104 is supported so (for eMMC) the caps2
+ * field can be promoted to support HS200.
+ */
+ cfg->host_caps |= MMC_MODE_HS200;
+ } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
+ cfg->host_caps |= MMC_MODE_UHS_SDR50;
+ }
+
+ if (caps_1 & SDHCI_SUPPORT_DDR50)
+ cfg->host_caps |= MMC_MODE_UHS_DDR50;
+
+ if (caps_1 & SDHCI_USE_SDR50_TUNING)
+ cfg->host_caps |= MMC_MODE_NEEDS_TUNING;
+
+ if (host->host_caps)
+ cfg->host_caps |= host->host_caps;
+
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+
++ if (caps_1 & SDHCI_SUPPORT_SDR104) {
++ cfg->host_caps |= MMC_MODE_UHS_SDR104 | MMC_MODE_UHS_SDR50;
++ /*
++ * SD3.0: SDR104 is supported so (for eMMC) the caps2
++ * field can be promoted to support HS200.
++ */
++ cfg->host_caps |= MMC_MODE_HS200;
++ } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
++ cfg->host_caps |= MMC_MODE_UHS_SDR50;
+ }
+
++ if (caps_1 & SDHCI_SUPPORT_DDR50)
++ cfg->host_caps |= MMC_MODE_UHS_DDR50;
++
++ if (caps_1 & SDHCI_USE_SDR50_TUNING)
++ cfg->host_caps |= MMC_MODE_NEEDS_TUNING;
++
+ if (host->host_caps)
+ cfg->host_caps |= host->host_caps;
+
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+
return 0;
}
#include <libfdt.h>
#include <malloc.h>
#include <sdhci.h>
+#include <mmc.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <zynqmp_tap_delay.h>
+#include "mmc_private.h"
+ DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
#endif
struct arasan_sdhci_plat {
struct mmc_config cfg;
struct mmc mmc;
+ unsigned int f_max;
};
+struct arasan_sdhci_priv {
+ struct sdhci_host *host;
+ u8 deviceid;
+ u8 bank;
+ u8 no_1p8;
+ bool pwrseq;
+};
+
+#if defined(CONFIG_ARCH_ZYNQMP)
+static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
+{
+ u16 clk;
+ unsigned long timeout;
+
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ clk &= ~(SDHCI_CLOCK_CARD_EN);
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ /* Issue DLL Reset */
+ zynqmp_dll_reset(deviceid);
+
+ /* Wait max 20 ms */
+ timeout = 100;
+ while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
+ & SDHCI_CLOCK_INT_STABLE)) {
+ if (timeout == 0) {
+ dev_err(mmc_dev(host->mmc),
+ ": Internal clock never stabilised.\n");
+ return;
+ }
+ timeout--;
+ udelay(1000);
+ }
+
+ clk |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+}
+
+static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+ struct mmc_cmd cmd;
+ struct mmc_data data;
+ u32 ctrl;
+ struct sdhci_host *host;
+ struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
+ u8 tuning_loop_counter = 40;
+ u8 deviceid;
+
+ debug("%s\n", __func__);
+
+ host = priv->host;
+ deviceid = priv->deviceid;
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
+ ctrl |= SDHCI_CTRL_EXEC_TUNING;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
+
+ mdelay(1);
+
+ arasan_zynqmp_dll_reset(host, deviceid);
+
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
+
+ do {
+ cmd.cmdidx = opcode;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = 0;
+
+ data.blocksize = 64;
+ data.blocks = 1;
+ data.flags = MMC_DATA_READ;
+
+ if (tuning_loop_counter-- == 0)
+ break;
+
+ if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
+ mmc->bus_width == 8)
+ data.blocksize = 128;
+
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
+ data.blocksize),
+ SDHCI_BLOCK_SIZE);
+ sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
+ sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
+
+ mmc_send_cmd(mmc, &cmd, NULL);
+ ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
+
+ if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+ udelay(1);
+
+ } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
+
+ if (tuning_loop_counter < 0) {
+ ctrl &= ~SDHCI_CTRL_TUNED_CLK;
+ sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
+ }
+
+ if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
+ debug("%s:Tuning failed\n", __func__);
+ return -1;
+ } else {
+ udelay(1);
+ arasan_zynqmp_dll_reset(host, deviceid);
+ }
+
+ /* Enable only interrupts served by the SD controller */
+ sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
+ SDHCI_INT_ENABLE);
+ /* Mask all sdhci interrupt sources */
+ sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
+
+ return 0;
+}
+
+static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
+{
+ struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
+ struct mmc *mmc = (struct mmc *)host->mmc;
+ u8 uhsmode;
+
+ if (mmc->is_uhs)
+ uhsmode = mmc->uhsmode;
+ else if (mmc->card_caps & MMC_MODE_HS)
+ uhsmode = MMC_TIMING_HS;
+ else if (mmc->card_caps & MMC_MODE_HS200)
+ uhsmode = MMC_TIMING_HS200;
+ else
+ return;
+
+ debug("%s, host:%s devId:%d, bank:%d, mode:%d\n", __func__, host->name,
+ priv->deviceid, priv->bank, uhsmode);
+ if ((uhsmode >= MMC_TIMING_UHS_SDR25) &&
+ (uhsmode <= MMC_TIMING_HS200))
+ arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
+ priv->bank);
+}
+#endif
+
static int arasan_sdhci_probe(struct udevice *dev)
{
struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct sdhci_host *host = dev_get_priv(dev);
+ struct arasan_sdhci_priv *priv = dev_get_priv(dev);
+ struct sdhci_host *host;
+ struct clk clk;
+ unsigned long clock;
int ret;
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get clock\n");
+ return ret;
+ }
+
+ clock = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(clock)) {
+ dev_err(dev, "failed to get rate\n");
+ return clock;
+ }
+ debug("%s: CLK %ld\n", __func__, clock);
+
+ ret = clk_enable(&clk);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+
+ host = priv->host;
+
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
- SDHCI_QUIRK_BROKEN_R1B;
+ SDHCI_QUIRK_BROKEN_R1B |
+ SDHCI_QUIRK_USE_ACMD12;
#ifdef CONFIG_ZYNQ_HISPD_BROKEN
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
#endif
- ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
+ if (priv->no_1p8)
+ host->quirks |= SDHCI_QUIRK_NO_1_8_V;
+
+ host->max_clk = clock;
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
CONFIG_ZYNQ_SDHCI_MIN_FREQ);
host->mmc = &plat->mmc;
if (ret)
static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
{
- struct sdhci_host *host = dev_get_priv(dev);
+ struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
+ struct arasan_sdhci_priv *priv = dev_get_priv(dev);
+
+ priv->host = calloc(1, sizeof(struct sdhci_host));
+ if (priv->host == NULL)
+ return -1;
- host->name = dev->name;
- host->ioaddr = (void *)devfdt_get_addr(dev);
+ priv->host->name = dev->name;
- priv->host->ioaddr = (void *)dev_get_addr(dev);
++ priv->host->ioaddr = (void *)devfdt_get_addr(dev);
- priv->deviceid = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->f_max = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);
+
++ priv->deviceid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "xlnx,device_id", -1);
- priv->bank = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
++ priv->bank = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "xlnx,mio_bank", -1);
- if (fdt_get_property(gd->fdt_blob, dev->of_offset, "no-1-8-v", NULL)
++
++ if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "no-1-8-v", NULL)
+#if defined(CONFIG_ARCH_ZYNQMP)
+ || (chip_id(VERSION) == ZYNQMP_SILICON_V1)
+#endif
+ )
+ priv->no_1p8 = 1;
+ else
+ priv->no_1p8 = 0;
+
- if (fdt_get_property(gd->fdt_blob, dev->of_offset, "mmc-pwrseq", NULL))
++ if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "mmc-pwrseq",
++ NULL))
+ priv->pwrseq = true;
+
return 0;
}
#define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */
#define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */
+#define ZYNQ_NAND_ROW_ADDR_CYCL_MASK 0x0F
+#define ZYNQ_NAND_COL_ADDR_CYCL_MASK 0xF0
+
+#define ZYNQ_NAND_MIO_NUM_NAND_8BIT 13
+#define ZYNQ_NAND_MIO_NUM_NAND_16BIT 8
+
+enum zynq_nand_bus_width {
+ NAND_BW_UNKNOWN = -1,
+ NAND_BW_8BIT,
+ NAND_BW_16BIT,
+};
+
+ #ifndef NAND_CMD_LOCK_TIGHT
+ #define NAND_CMD_LOCK_TIGHT 0x2c
+ #endif
+
+ #ifndef NAND_CMD_LOCK_STATUS
+ #define NAND_CMD_LOCK_STATUS 0x7a
+ #endif
+
/* SMC register set */
struct zynq_nand_smc_regs {
u32 csr; /* 0x00 */
return 0;
}
- static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
+static int zynq_nand_check_is_16bit_bw_flash(void)
+{
+ int is_16bit_bw = NAND_BW_UNKNOWN;
+ int mio_num_8bit = 0, mio_num_16bit = 0;
+
+ mio_num_8bit = zynq_slcr_get_mio_pin_status("nand8");
+ if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT)
+ is_16bit_bw = NAND_BW_8BIT;
+
+ mio_num_16bit = zynq_slcr_get_mio_pin_status("nand16");
+ if ((mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT) &&
+ (mio_num_16bit == ZYNQ_NAND_MIO_NUM_NAND_16BIT))
+ is_16bit_bw = NAND_BW_16BIT;
+
+ return is_16bit_bw;
+}
+
+ int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
{
struct zynq_nand_info *xnand;
struct mtd_info *mtd;
}
xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
+ mtd = get_nand_dev_by_index(0);
+ mtd = nand_to_mtd(nand_chip);
nand_chip->priv = xnand;
mtd->priv = nand_chip;
Bank/Extended address registers are used to access the flash
which has size > 16MiB in 3-byte addressing.
+ config SF_DUAL_FLASH
+ bool "SPI DUAL flash memory support"
+ depends on SPI_FLASH
+ help
+ Enable this option to support two flash memories connected to a single
+ controller. Currently Xilinx Zynq qspi supports this.
+
++config SPI_GENERIC
++ bool "SPI flash support"
++ depends on ARCH_ZYNQMP
++ help
++ Enable the generic SPI flash controller support.
++
if SPI_FLASH
config SPI_FLASH_ATMEL
#endif
#ifdef CONFIG_SPI_FLASH_BAR
+ /*
+ * This "clean_bar" is necessary in a situation when one was accessing
+ * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
+ *
+ * After it the BA24 bit shall be cleared to allow access to correct
+ * memory region after SW reset (by calling "reset" command).
+ *
+ * Otherwise, the BA24 bit may be left set and then after reset, the
+ * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
+ */
+ static int clean_bar(struct spi_flash *flash)
+ {
+ u8 cmd, bank_sel = 0;
+
+ if (flash->bank_curr == 0)
+ return 0;
+ cmd = flash->bank_write_cmd;
+
+ return spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
+ }
+
static int write_bar(struct spi_flash *flash, u32 offset)
{
- u8 cmd, bank_sel;
+ u8 cmd, bank_sel, upage_curr;
int ret;
bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
data += read_len;
}
+#ifdef CONFIG_SF_DUAL_FLASH
+ if (flash->dual_flash == SF_DUAL_PARALLEL_FLASH) {
+ if (moveoffs) {
+ data = tempbuf + 1;
+ memcpy(tempbuf, data, length);
+ }
+ }
+#endif
+
+ spi->dummy_bytes = 0;
+
+ #ifdef CONFIG_SPI_FLASH_BAR
+ ret = clean_bar(flash);
+ #endif
+
free(cmd);
return ret;
}
}
}
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash,
+ int enable, u8 idcode0)
+{
+ int ret;
+ u8 cmd, bar;
+ bool need_wren = false;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: unable to claim SPI bus\n");
+ return ret;
+ }
+
+ switch (idcode0) {
+ case SPI_FLASH_CFI_MFR_STMICRO:
+ /* Some Micron need WREN command; all will accept it */
+ need_wren = true;
+ case SPI_FLASH_CFI_MFR_MACRONIX:
+ case SPI_FLASH_CFI_MFR_WINBOND:
+ if (need_wren)
+ spi_flash_cmd_write_enable(flash);
+
+ cmd = enable ? CMD_ENTER_4B_ADDR : CMD_EXIT_4B_ADDR;
+ ret = spi_flash_cmd(flash->spi, cmd, NULL, 0);
+ if (need_wren)
+ spi_flash_cmd_write_disable(flash);
+
+ break;
+ default:
++#ifdef CONFIG_SPI_FLASH_BAR
+ /* Spansion style */
+ bar = enable << 7;
+ cmd = CMD_BANKADDR_BRWR;
+ ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &bar, 1);
++#else
++ puts("SF: Bank Address is not set\n");
++ ret = -EINVAL;
++#endif
+ }
+
+ spi_release_bus(flash->spi);
+
+ return ret;
+}
+
#if CONFIG_IS_ENABLED(OF_CONTROL)
- int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
+ int spi_flash_decode_fdt(struct spi_flash *flash)
{
#ifdef CONFIG_DM_SPI_FLASH
fdt_addr_t addr;
if (IS_ERR_OR_NULL(info))
return -ENOENT;
- /* Flash powers up read-only, so clear BP# bits */
+ /*
+ * Flash powers up read-only, so clear BP# bits.
+ *
+ * Note on some flash (like Macronix), QE (quad enable) bit is in the
+ * same status register as BP# bits, and we need preserve its original
+ * value during a reboot cycle as this is required by some platforms
+ * (like Intel ICH SPI controller working under descriptor mode).
+ */
if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
- JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX ||
- JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST)
+ (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) ||
+ (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX)) {
+ u8 sr = 0;
+
+ if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) {
+ read_sr(flash, &sr);
+ sr &= STATUS_QEB_MXIC;
+ }
++
+#ifdef CONFIG_SPI_GENERIC
- {
+ flash->dual_flash = flash->spi->option;
+ if (flash->dual_flash & SF_DUAL_PARALLEL_FLASH)
+ flash->spi->flags |= SPI_XFER_LOWER;
+#endif
- write_sr(flash, 0);
+ write_sr(flash, sr);
+#ifdef CONFIG_SPI_GENERIC
+ if (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) {
+ flash->spi->flags |= SPI_XFER_UPPER;
+ write_sr(flash, 0);
+ }
- }
+#endif
+ }
flash->name = info->name;
flash->memory_map = spi->memory_map;
struct xilinx_spi_regs *regs;
unsigned int freq;
unsigned int mode;
+ unsigned int fifo_depth;
};
-static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
+static int xilinx_spi_child_pre_probe(struct udevice *bus)
+{
+ struct spi_slave *slave = dev_get_parent_priv(bus);
+ struct udevice *dev = dev_get_parent(bus);
+ int spimode;
+
- spimode = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "xlnx,spi-mode",
++ spimode = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "xlnx,spi-mode",
+ -1);
+
+ if (spimode == XILINX_SPI_QUAD_MODE)
+ slave->mode = SPI_RX_QUAD;
+
+ return 0;
+}
+
static int xilinx_spi_probe(struct udevice *bus)
{
struct xilinx_spi_priv *priv = dev_get_priv(bus);
.set_mode = xilinx_spi_set_mode,
};
- priv->regs = (struct xilinx_spi_regs *)dev_get_addr(bus);
+
+static int xilinx_spi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+
- priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
++ priv->regs = (struct xilinx_spi_regs *)devfdt_get_addr(bus);
+
+ debug("%s: regs=%p\n", __func__, priv->regs);
+
++ priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
+ "fifo-size", 0);
+
+ return 0;
+}
+
static const struct udevice_id xilinx_spi_ids[] = {
{ .compatible = "xlnx,xps-spi-2.00.a" },
{ .compatible = "xlnx,xps-spi-2.00.b" },
static int zynq_qspi_ofdata_to_platdata(struct udevice *bus)
{
struct zynq_qspi_platdata *plat = bus->platdata;
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(bus);
+ int is_dual;
+ u32 mode = 0;
+ int offset;
+ u32 value;
+
+ debug("%s\n", __func__);
+ plat->regs = (struct zynq_qspi_regs *)ZYNQ_QSPI_BASEADDR;
+
- is_dual = fdtdec_get_int(gd->fdt_blob, bus->of_offset, "is-dual", -1);
++ is_dual = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "is-dual", -1);
+ if (is_dual < 0)
+ plat->is_dual = SF_SINGLE_FLASH;
+ else if (is_dual == 1)
+ plat->is_dual = SF_DUAL_PARALLEL_FLASH;
+ else
- if (fdtdec_get_int(gd->fdt_blob, bus->of_offset,
++ if (fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
+ "is-stacked", -1) < 0)
+ plat->is_dual = SF_SINGLE_FLASH;
+ else
+ plat->is_dual = SF_DUAL_STACKED_FLASH;
- offset = fdt_first_subnode(gd->fdt_blob, bus->of_offset);
- plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
- node, "reg");
++ offset = fdt_first_subnode(gd->fdt_blob, dev_of_offset(bus));
- /* FIXME: Use 166MHz as a suitable default */
- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
- 166666666);
- plat->speed_hz = plat->frequency / 2;
+ value = fdtdec_get_uint(gd->fdt_blob, offset, "spi-rx-bus-width", 1);
+ switch (value) {
+ case 1:
+ break;
+ case 2:
+ mode |= SPI_RX_DUAL;
+ break;
+ case 4:
+ mode |= SPI_RX_QUAD;
+ break;
+ default:
+ printf("Invalid spi-rx-bus-width %d\n", value);
+ break;
+ }
+
+ value = fdtdec_get_uint(gd->fdt_blob, offset, "spi-tx-bus-width", 1);
+ switch (value) {
+ case 1:
+ break;
+ case 2:
+ mode |= SPI_TX_DUAL;
+ break;
+ case 4:
+ mode |= SPI_TX_QUAD;
+ break;
+ default:
+ printf("Invalid spi-tx-bus-width %d\n", value);
+ break;
+ }
+
+ plat->tx_rx_mode = mode;
- debug("%s: regs=%p max-frequency=%d\n", __func__,
- plat->regs, plat->frequency);
+ plat->frequency = 166666666;
+ plat->speed_hz = plat->frequency / 2;
return 0;
}
--- /dev/null
- plat->regs = (struct zynqmp_qspi_regs *)(dev_get_addr(bus) + 0x100);
- plat->dma_regs = (struct zynqmp_qspi_dma_regs *)(dev_get_addr(bus) +
+/*
+ * (C) Copyright 2014 - 2015 Xilinx
+ *
+ * Xilinx ZynqMP Quad-SPI(QSPI) controller driver (master mode only)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <ubi_uboot.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clk.h>
+#include "../mtd/spi/sf_internal.h"
+#include <clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ZYNQMP_QSPI_GFIFO_STRT_MODE_MASK (1 << 29)
+#define ZYNQMP_QSPI_CONFIG_MODE_EN_MASK (3 << 30)
+#define ZYNQMP_QSPI_CONFIG_DMA_MODE (2 << 30)
+#define ZYNQMP_QSPI_CONFIG_CPHA_MASK (1 << 2)
+#define ZYNQMP_QSPI_CONFIG_CPOL_MASK (1 << 1)
+
+/* QSPI MIO's count for different connection topologies */
+#define ZYNQMP_QSPI_MIO_NUM_QSPI0 6
+#define ZYNQMP_QSPI_MIO_NUM_QSPI1 5
+#define ZYNQMP_QSPI_MIO_NUM_QSPI1_CS 1
+
+/*
+ * QSPI Interrupt Registers bit Masks
+ *
+ * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
+ * bit definitions.
+ */
+#define ZYNQMP_QSPI_IXR_TXNFULL_MASK 0x00000004 /* QSPI TX FIFO Overflow */
+#define ZYNQMP_QSPI_IXR_TXFULL_MASK 0x00000008 /* QSPI TX FIFO is full */
+#define ZYNQMP_QSPI_IXR_RXNEMTY_MASK 0x00000010 /* QSPI RX FIFO Not Empty */
+#define ZYNQMP_QSPI_IXR_GFEMTY_MASK 0x00000080 /* QSPI Generic FIFO Empty */
+#define ZYNQMP_QSPI_IXR_ALL_MASK (ZYNQMP_QSPI_IXR_TXNFULL_MASK | \
+ ZYNQMP_QSPI_IXR_RXNEMTY_MASK)
+
+/*
+ * QSPI Enable Register bit Masks
+ *
+ * This register is used to enable or disable the QSPI controller
+ */
+#define ZYNQMP_QSPI_ENABLE_ENABLE_MASK 0x00000001 /* QSPI Enable Bit Mask */
+
+#define ZYNQMP_QSPI_GFIFO_LOW_BUS (1 << 14)
+#define ZYNQMP_QSPI_GFIFO_CS_LOWER (1 << 12)
+#define ZYNQMP_QSPI_GFIFO_UP_BUS (1 << 15)
+#define ZYNQMP_QSPI_GFIFO_CS_UPPER (1 << 13)
+#define ZYNQMP_QSPI_SPI_MODE_QSPI (3 << 10)
+#define ZYNQMP_QSPI_SPI_MODE_SPI (1 << 10)
+#define ZYNQMP_QSPI_SPI_MODE_DUAL_SPI (2 << 10)
+#define ZYNQMP_QSPI_IMD_DATA_CS_ASSERT 5
+#define ZYNQMP_QSPI_IMD_DATA_CS_DEASSERT 5
+#define ZYNQMP_QSPI_GFIFO_TX (1 << 16)
+#define ZYNQMP_QSPI_GFIFO_RX (1 << 17)
+#define ZYNQMP_QSPI_GFIFO_STRIPE_MASK (1 << 18)
+#define ZYNQMP_QSPI_GFIFO_IMD_MASK 0xFF
+#define ZYNQMP_QSPI_GFIFO_EXP_MASK (1 << 9)
+#define ZYNQMP_QSPI_GFIFO_DATA_XFR_MASK (1 << 8)
+#define ZYNQMP_QSPI_STRT_GEN_FIFO (1 << 28)
+#define ZYNQMP_QSPI_GEN_FIFO_STRT_MOD (1 << 29)
+#define ZYNQMP_QSPI_GFIFO_WP_HOLD (1 << 19)
+#define ZYNQMP_QSPI_BAUD_DIV_MASK (7 << 3)
+#define ZYNQMP_QSPI_DFLT_BAUD_RATE_DIV (1 << 3)
+#define ZYNQMP_QSPI_GFIFO_ALL_INT_MASK 0xFBE
+#define ZYNQMP_QSPI_DMA_DST_I_STS_DONE (1 << 1)
+#define ZYNQMP_QSPI_DMA_DST_I_STS_MASK 0xFE
+#define MODEBITS 0x6
+
+#define QUAD_OUT_READ_CMD 0x6B
+#define QUAD_PAGE_PROGRAM_CMD 0x32
+#define DUAL_OUTPUT_FASTRD_CMD 0x3B
+
+#define ZYNQMP_QSPI_GFIFO_SELECT (1 << 0)
+
+#define ZYNQMP_QSPI_FIFO_THRESHOLD 1
+
+#define SPI_XFER_ON_BOTH 0
+#define SPI_XFER_ON_LOWER 1
+#define SPI_XFER_ON_UPPER 2
+
+#define ZYNQMP_QSPI_DMA_ALIGN 0x4
+#define ZYNQMP_QSPI_MAX_BAUD_RATE_VAL 7
+#define ZYNQMP_QSPI_DFLT_BAUD_RATE_VAL 2
+
+#define ZYNQMP_QSPI_TIMEOUT 100000000
+
+/* QSPI register offsets */
+struct zynqmp_qspi_regs {
+ u32 confr; /* 0x00 */
+ u32 isr; /* 0x04 */
+ u32 ier; /* 0x08 */
+ u32 idisr; /* 0x0C */
+ u32 imaskr; /* 0x10 */
+ u32 enbr; /* 0x14 */
+ u32 dr; /* 0x18 */
+ u32 txd0r; /* 0x1C */
+ u32 drxr; /* 0x20 */
+ u32 sicr; /* 0x24 */
+ u32 txftr; /* 0x28 */
+ u32 rxftr; /* 0x2C */
+ u32 gpior; /* 0x30 */
+ u32 reserved0; /* 0x34 */
+ u32 lpbkdly; /* 0x38 */
+ u32 reserved1; /* 0x3C */
+ u32 genfifo; /* 0x40 */
+ u32 gqspisel; /* 0x44 */
+ u32 reserved2; /* 0x48 */
+ u32 gqfifoctrl; /* 0x4C */
+ u32 gqfthr; /* 0x50 */
+ u32 gqpollcfg; /* 0x54 */
+ u32 gqpollto; /* 0x58 */
+ u32 gqxfersts; /* 0x5C */
+ u32 gqfifosnap; /* 0x60 */
+ u32 gqrxcpy; /* 0x64 */
+ u32 reserved3[36]; /* 0x68 */
+ u32 gqspidlyadj; /* 0xF8 */
+};
+
+struct zynqmp_qspi_dma_regs {
+ u32 dmadst; /* 0x00 */
+ u32 dmasize; /* 0x04 */
+ u32 dmasts; /* 0x08 */
+ u32 dmactrl; /* 0x0C */
+ u32 reserved0; /* 0x10 */
+ u32 dmaisr; /* 0x14 */
+ u32 dmaier; /* 0x18 */
+ u32 dmaidr; /* 0x1C */
+ u32 dmaimr; /* 0x20 */
+ u32 dmactrl2; /* 0x24 */
+ u32 dmadstmsb; /* 0x28 */
+};
+
+struct zynqmp_qspi_platdata {
+ struct zynqmp_qspi_regs *regs;
+ struct zynqmp_qspi_dma_regs *dma_regs;
+ u32 frequency;
+ u32 speed_hz;
+ unsigned int is_dual;
+ unsigned int tx_rx_mode;
+};
+
+struct zynqmp_qspi_priv {
+ struct zynqmp_qspi_regs *regs;
+ struct zynqmp_qspi_dma_regs *dma_regs;
+ u8 mode;
+ const void *tx_buf;
+ void *rx_buf;
+ unsigned len;
+ int bytes_to_transfer;
+ int bytes_to_receive;
+ unsigned int is_inst;
+ unsigned int is_dual;
+ unsigned int u_page;
+ unsigned int bus;
+ unsigned int stripe;
+ unsigned cs_change:1;
+ unsigned int dummy_bytes;
+ unsigned int tx_rx_mode;
+};
+
+static u8 last_cmd;
+
+static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct zynqmp_qspi_platdata *plat = bus->platdata;
+ int is_dual;
+ u32 mode = 0;
+ int offset;
+ u32 value;
+ int ret;
+ struct clk clk;
+ unsigned long clock;
+
+ debug("%s\n", __func__);
+
- is_dual = fdtdec_get_int(gd->fdt_blob, bus->of_offset, "is-dual", -1);
++ plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) + 0x100);
++ plat->dma_regs = (struct zynqmp_qspi_dma_regs *)(devfdt_get_addr(bus) +
+ 0x800);
+
+ ret = clk_get_by_index(bus, 0, &clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get clock\n");
+ return ret;
+ }
+
+ clock = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(clock)) {
+ dev_err(dev, "failed to get rate\n");
+ return clock;
+ }
+ debug("%s: CLK %ld\n", __func__, clock);
+
+ ret = clk_enable(&clk);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+
- if (fdtdec_get_int(gd->fdt_blob, bus->of_offset,
++ is_dual = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "is-dual", -1);
+ if (is_dual < 0)
+ plat->is_dual = SF_SINGLE_FLASH;
+ else if (is_dual == 1)
+ plat->is_dual = SF_DUAL_PARALLEL_FLASH;
+ else
- offset = fdt_first_subnode(gd->fdt_blob, bus->of_offset);
++ if (fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
+ "is-stacked", -1) < 0)
+ plat->is_dual = SF_SINGLE_FLASH;
+ else
+ plat->is_dual = SF_DUAL_STACKED_FLASH;
+
- value = fdtdec_get_uint(gd->fdt_blob, offset, "spi-tx-bus-width", 1);
++ offset = fdt_first_subnode(gd->fdt_blob, dev_of_offset(bus));
+
+ value = fdtdec_get_uint(gd->fdt_blob, offset, "spi-rx-bus-width", 1);
+ switch (value) {
+ case 1:
+ break;
+ case 2:
+ mode |= SPI_RX_DUAL;
+ break;
+ case 4:
+ mode |= SPI_RX_QUAD;
+ break;
+ default:
+ printf("Invalid spi-rx-bus-width %d\n", value);
+ break;
+ }
+
++ value = dev_read_u32_default(bus, "spi-tx-bus-width", 1);
+ switch (value) {
+ case 1:
+ break;
+ case 2:
+ mode |= SPI_TX_DUAL;
+ break;
+ case 4:
+ mode |= SPI_TX_QUAD;
+ break;
+ default:
+ printf("Invalid spi-tx-bus-width %d\n", value);
+ break;
+ }
+
+ plat->tx_rx_mode = mode;
+
+ plat->frequency = clock;
+ plat->speed_hz = plat->frequency;
+
+ return 0;
+}
+
+static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
+{
+ u32 config_reg;
+ struct zynqmp_qspi_regs *regs = priv->regs;
+
+ writel(ZYNQMP_QSPI_GFIFO_SELECT, ®s->gqspisel);
+ writel(ZYNQMP_QSPI_GFIFO_ALL_INT_MASK, ®s->idisr);
+ writel(ZYNQMP_QSPI_FIFO_THRESHOLD, ®s->txftr);
+ writel(ZYNQMP_QSPI_FIFO_THRESHOLD, ®s->rxftr);
+ writel(ZYNQMP_QSPI_GFIFO_ALL_INT_MASK, ®s->isr);
+
+ config_reg = readl(®s->confr);
+ config_reg &= ~(ZYNQMP_QSPI_GFIFO_STRT_MODE_MASK |
+ ZYNQMP_QSPI_CONFIG_MODE_EN_MASK);
+ config_reg |= ZYNQMP_QSPI_CONFIG_DMA_MODE |
+ ZYNQMP_QSPI_GFIFO_WP_HOLD |
+ ZYNQMP_QSPI_DFLT_BAUD_RATE_DIV;
+ writel(config_reg, ®s->confr);
+
+ writel(ZYNQMP_QSPI_ENABLE_ENABLE_MASK, ®s->enbr);
+}
+
+static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
+{
+ u32 gqspi_fifo_reg = 0;
+
+ if (priv->is_dual == SF_DUAL_PARALLEL_FLASH) {
+ if (priv->bus == SPI_XFER_ON_BOTH)
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS |
+ ZYNQMP_QSPI_GFIFO_UP_BUS |
+ ZYNQMP_QSPI_GFIFO_CS_UPPER |
+ ZYNQMP_QSPI_GFIFO_CS_LOWER;
+ else if (priv->bus == SPI_XFER_ON_LOWER)
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS |
+ ZYNQMP_QSPI_GFIFO_CS_UPPER |
+ ZYNQMP_QSPI_GFIFO_CS_LOWER;
+ else if (priv->bus == SPI_XFER_ON_UPPER)
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_UP_BUS |
+ ZYNQMP_QSPI_GFIFO_CS_LOWER |
+ ZYNQMP_QSPI_GFIFO_CS_UPPER;
+ else
+ debug("Wrong Bus selection:0x%x\n", priv->bus);
+ } else {
+ if (priv->u_page)
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS |
+ ZYNQMP_QSPI_GFIFO_CS_UPPER;
+ else
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS |
+ ZYNQMP_QSPI_GFIFO_CS_LOWER;
+ }
+ return gqspi_fifo_reg;
+}
+
+static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
+ u32 gqspi_fifo_reg)
+{
+ struct zynqmp_qspi_regs *regs = priv->regs;
+ u32 reg;
+
+ do {
+ reg = readl(®s->isr);
+ } while (!(reg & ZYNQMP_QSPI_IXR_GFEMTY_MASK));
+
+ writel(gqspi_fifo_reg, ®s->genfifo);
+}
+
+static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
+{
+ u32 gqspi_fifo_reg = 0;
+
+ if (is_on) {
+ gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
+ gqspi_fifo_reg |= ZYNQMP_QSPI_SPI_MODE_SPI |
+ ZYNQMP_QSPI_IMD_DATA_CS_ASSERT;
+ } else {
+ if (priv->is_dual == SF_DUAL_PARALLEL_FLASH)
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_UP_BUS |
+ ZYNQMP_QSPI_GFIFO_LOW_BUS;
+ else if (priv->u_page)
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_UP_BUS;
+ else
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS;
+ gqspi_fifo_reg |= ZYNQMP_QSPI_IMD_DATA_CS_DEASSERT;
+ }
+
+ debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
+
+ zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
+}
+
+#define GQSPI_BAUD_DIV_SHIFT 2
+#define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5
+#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x2
+#define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3
+#define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3
+#define GQSPI_USE_DATA_DLY 0x1
+#define GQSPI_USE_DATA_DLY_SHIFT 31
+#define GQSPI_DATA_DLY_ADJ_VALUE 0x2
+#define GQSPI_DATA_DLY_ADJ_SHIFT 28
+#define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1
+#define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2
+#define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8
+#define IOU_TAPDLY_BYPASS_OFST 0xFF180390
+#define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020
+#define GQSPI_FREQ_40MHZ 40000000
+#define GQSPI_FREQ_100MHZ 100000000
+#define GQSPI_FREQ_150MHZ 150000000
+#define IOU_TAPDLY_BYPASS_MASK 0x7
+
+void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
+{
+ struct zynqmp_qspi_platdata *plat = bus->platdata;
+ struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+ struct zynqmp_qspi_regs *regs = priv->regs;
+ u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
+ u32 reqhz = 0;
+
+ clk_rate = plat->frequency;
+ reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
+
+ debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
+ __func__, reqhz, clk_rate, baudrateval);
+
+ if (reqhz < GQSPI_FREQ_40MHZ) {
+ zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
+ tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+ TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
+ } else if (reqhz < GQSPI_FREQ_100MHZ) {
+ zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
+ tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+ TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
+ lpbkdlyadj = readl(®s->lpbkdly);
+ lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
+ datadlyadj = readl(®s->gqspidlyadj);
+ datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
+ | (GQSPI_DATA_DLY_ADJ_VALUE <<
+ GQSPI_DATA_DLY_ADJ_SHIFT));
+ } else if (reqhz < GQSPI_FREQ_150MHZ) {
+ lpbkdlyadj = readl(®s->lpbkdly);
+ lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK) |
+ GQSPI_LPBK_DLY_ADJ_DLY_0);
+ }
+
+ zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK,
+ tapdlybypass);
+ writel(lpbkdlyadj, ®s->lpbkdly);
+ writel(datadlyadj, ®s->gqspidlyadj);
+}
+
+static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
+{
+ struct zynqmp_qspi_platdata *plat = bus->platdata;
+ struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+ struct zynqmp_qspi_regs *regs = priv->regs;
+ uint32_t confr;
+ u8 baud_rate_val = 0;
+
+ debug("%s\n", __func__);
+ if (speed > plat->frequency)
+ speed = plat->frequency;
+
+ /* Set the clock frequency */
+ confr = readl(®s->confr);
+ if (speed == 0) {
+ /* Set baudrate x8, if the freq is 0 */
+ baud_rate_val = ZYNQMP_QSPI_DFLT_BAUD_RATE_VAL;
+ } else if (plat->speed_hz != speed) {
+ while ((baud_rate_val < 8) &&
+ ((plat->frequency /
+ (2 << baud_rate_val)) > speed))
+ baud_rate_val++;
+
+ if (baud_rate_val > ZYNQMP_QSPI_MAX_BAUD_RATE_VAL)
+ baud_rate_val = ZYNQMP_QSPI_DFLT_BAUD_RATE_VAL;
+
+ plat->speed_hz = plat->frequency / (2 << baud_rate_val);
+ }
+ confr &= ~ZYNQMP_QSPI_BAUD_DIV_MASK;
+ confr |= (baud_rate_val << 3);
+ writel(confr, ®s->confr);
+
+ zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
+ debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
+
+ return 0;
+}
+
+static int zynqmp_qspi_child_pre_probe(struct udevice *bus)
+{
+ struct spi_slave *slave = dev_get_parent_priv(bus);
+ struct zynqmp_qspi_priv *priv = dev_get_priv(bus->parent);
+ struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus->parent);
+
+ slave->option = priv->is_dual;
+ slave->mode = plat->tx_rx_mode;
+ slave->bytemode = SPI_4BYTE_MODE;
+
+ return 0;
+}
+
+static int zynqmp_qspi_probe(struct udevice *bus)
+{
+ struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus);
+ struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+
+ debug("zynqmp_qspi_probe: bus:%p, priv:%p \n", bus, priv);
+
+ priv->regs = plat->regs;
+ priv->dma_regs = plat->dma_regs;
+ priv->is_dual = plat->is_dual;
+ priv->tx_rx_mode = plat->tx_rx_mode;
+
+ if (priv->is_dual == -1) {
+ debug("%s: No QSPI device detected based on MIO settings\n",
+ __func__);
+ return -1;
+ }
+
+ /* init the zynq spi hw */
+ zynqmp_qspi_init_hw(priv);
+
+ return 0;
+}
+
+static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
+{
+ struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+ struct zynqmp_qspi_regs *regs = priv->regs;
+ uint32_t confr;
+
+ debug("%s\n", __func__);
+ /* Set the SPI Clock phase and polarities */
+ confr = readl(®s->confr);
+ confr &= ~(ZYNQMP_QSPI_CONFIG_CPHA_MASK |
+ ZYNQMP_QSPI_CONFIG_CPOL_MASK);
+
+ if (priv->mode & SPI_CPHA)
+ confr |= ZYNQMP_QSPI_CONFIG_CPHA_MASK;
+ if (priv->mode & SPI_CPOL)
+ confr |= ZYNQMP_QSPI_CONFIG_CPOL_MASK;
+
+ //writel(confr, ®s->confr);
+ priv->mode = mode;
+
+ debug("regs=%p, mode=%d\n", priv->regs, priv->mode);
+
+ return 0;
+}
+
+
+static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
+{
+ u32 data;
+ u32 timeout = ZYNQMP_QSPI_TIMEOUT;
+ struct zynqmp_qspi_regs *regs = priv->regs;
+ u32 *buf = (u32 *)priv->tx_buf;
+ u32 len = size;
+
+ debug("TxFIFO: 0x%x, size: 0x%x\n", readl(®s->isr),
+ size);
+
+ while (size && timeout) {
+ if (readl(®s->isr) &
+ ZYNQMP_QSPI_IXR_TXNFULL_MASK) {
+ if (size >= 4) {
+ writel(*buf, ®s->txd0r);
+ buf++;
+ size -= 4;
+ } else {
+ switch (size) {
+ case 1:
+ data = *((u8 *)buf);
+ buf += 1;
+ data |= 0xFFFFFF00;
+ break;
+ case 2:
+ data = *((u16 *)buf);
+ buf += 2;
+ data |= 0xFFFF0000;
+ break;
+ case 3:
+ data = *((u16 *)buf);
+ buf += 2;
+ data |= (*((u8 *)buf) << 16);
+ buf += 1;
+ data |= 0xFF000000;
+ break;
+ }
+ writel(data, ®s->txd0r);
+ size = 0;
+ }
+ } else {
+ udelay(1);
+ timeout--;
+ }
+ }
+ if (!timeout) {
+ printf("zynqmp_qspi_fill_tx_fifo: Timeout\n");
+ return -1;
+ }
+
+ priv->tx_buf += len;
+ return 0;
+}
+
+static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
+{
+ u8 command = 1;
+ u32 gen_fifo_cmd;
+ u32 bytecount = 0;
+
+ if (priv->dummy_bytes)
+ priv->len -= priv->dummy_bytes;
+
+ while (priv->len) {
+ gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
+ gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_TX;
+
+ if (command) {
+ command = 0;
+ last_cmd = *(u8 *)priv->tx_buf;
+ }
+
+ gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_SPI;
+ gen_fifo_cmd |= *(u8 *)priv->tx_buf;
+ bytecount++;
+ priv->len--;
+ priv->tx_buf = (u8 *)priv->tx_buf + 1;
+
+ debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
+
+ zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
+ }
+
+ if (priv->dummy_bytes) {
+ gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
+ gen_fifo_cmd &= ~(ZYNQMP_QSPI_GFIFO_TX | ZYNQMP_QSPI_GFIFO_RX);
+ if (priv->tx_rx_mode & SPI_RX_QUAD)
+ gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_QSPI;
+ else if (priv->tx_rx_mode & SPI_RX_DUAL)
+ gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_DUAL_SPI;
+ else
+ gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_SPI;
+ gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_DATA_XFR_MASK;
+ gen_fifo_cmd |= (priv->dummy_bytes * 8);
+ zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
+ }
+}
+
+static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
+ u32 *gen_fifo_cmd)
+{
+ u32 expval = 8;
+ u32 len;
+
+ while (1) {
+ if (priv->len > 255) {
+ if (priv->len & (1 << expval)) {
+ *gen_fifo_cmd &= ~ZYNQMP_QSPI_GFIFO_IMD_MASK;
+ *gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_EXP_MASK;
+ *gen_fifo_cmd |= expval;
+ priv->len -= (1 << expval);
+ return expval;
+ }
+ expval++;
+ } else {
+ *gen_fifo_cmd &= ~(ZYNQMP_QSPI_GFIFO_IMD_MASK |
+ ZYNQMP_QSPI_GFIFO_EXP_MASK);
+ *gen_fifo_cmd |= (u8)priv->len;
+ len = (u8)priv->len;
+ priv->len = 0;
+ return len;
+ }
+ }
+}
+
+static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
+{
+ u32 gen_fifo_cmd;
+ u32 len;
+ int ret = 0;
+
+ gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
+ gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_TX |
+ ZYNQMP_QSPI_GFIFO_DATA_XFR_MASK;
+
+ if (priv->stripe)
+ gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_STRIPE_MASK;
+
+ if (last_cmd == QUAD_PAGE_PROGRAM_CMD)
+ gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_QSPI;
+ else
+ gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_SPI;
+
+ while (priv->len) {
+ len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
+ zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
+
+ debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
+
+ if (gen_fifo_cmd & ZYNQMP_QSPI_GFIFO_EXP_MASK)
+ ret = zynqmp_qspi_fill_tx_fifo(priv,
+ 1 << len);
+ else
+ ret = zynqmp_qspi_fill_tx_fifo(priv,
+ len);
+
+ if (ret)
+ return ret;
+ }
+ return ret;
+}
+
+static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
+ u32 gen_fifo_cmd, u32 *buf)
+{
+ u32 addr;
+ u32 size, len;
+ u32 timeout = ZYNQMP_QSPI_TIMEOUT;
+ u32 actuallen = priv->len;
+ struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
+
+ writel((unsigned long)buf, &dma_regs->dmadst);
+ writel(roundup(priv->len, 4), &dma_regs->dmasize);
+ writel(ZYNQMP_QSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
+ addr = (unsigned long)buf;
+ size = roundup(priv->len, ARCH_DMA_MINALIGN);
+ flush_dcache_range(addr, addr+size);
+
+ while (priv->len) {
+ len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
+ if (!(gen_fifo_cmd & ZYNQMP_QSPI_GFIFO_EXP_MASK) &&
+ (len % 4)) {
+ gen_fifo_cmd &= ~(0xFF);
+ gen_fifo_cmd |= (len/4 + 1) * 4;
+ }
+ zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
+
+ debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
+ }
+
+ while (timeout) {
+ if (readl(&dma_regs->dmaisr) &
+ ZYNQMP_QSPI_DMA_DST_I_STS_DONE) {
+ writel(ZYNQMP_QSPI_DMA_DST_I_STS_DONE,
+ &dma_regs->dmaisr);
+ break;
+ }
+ udelay(1);
+ timeout--;
+ }
+
+ debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
+ (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
+ actuallen);
+ if (!timeout) {
+ printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
+ return -1;
+ }
+
+ if (buf != priv->rx_buf)
+ memcpy(priv->rx_buf, buf, actuallen);
+
+ return 0;
+}
+
+static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
+{
+ u32 gen_fifo_cmd;
+ u32 *buf;
+ u32 actuallen = priv->len;
+
+ gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
+ gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_RX |
+ ZYNQMP_QSPI_GFIFO_DATA_XFR_MASK;
+
+ if (last_cmd == QUAD_OUT_READ_CMD)
+ gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_QSPI;
+ else if (last_cmd == DUAL_OUTPUT_FASTRD_CMD)
+ gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_DUAL_SPI;
+ else
+ gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_SPI;
+
+ if (priv->stripe)
+ gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_STRIPE_MASK;
+
+ /*
+ * Check if receive buffer is aligned to 4 byte and length
+ * is multiples of four byte as we are using dma to receive.
+ */
+ if (!((unsigned long)priv->rx_buf & (ZYNQMP_QSPI_DMA_ALIGN - 1)) &&
+ !(actuallen % ZYNQMP_QSPI_DMA_ALIGN)) {
+ buf = (u32 *)priv->rx_buf;
+ return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
+ }
+
+ ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len,
+ ZYNQMP_QSPI_DMA_ALIGN));
+ buf = (u32 *)tmp;
+ return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
+}
+
+static int zynqmp_qspi_start_transfer(struct zynqmp_qspi_priv *priv)
+{
+ int ret = 0;
+
+ if (priv->is_inst) {
+ if (priv->tx_buf)
+ zynqmp_qspi_genfifo_cmd(priv);
+ else
+ ret = -1;
+ } else {
+ if (priv->tx_buf)
+ ret = zynqmp_qspi_genfifo_fill_tx(priv);
+ else if (priv->rx_buf)
+ ret = zynqmp_qspi_genfifo_fill_rx(priv);
+ else
+ ret = -1;
+ }
+ return ret;
+}
+
+static int zynqmp_qspi_transfer(struct zynqmp_qspi_priv *priv)
+{
+ static unsigned cs_change = 1;
+ int status = 0;
+
+ debug("%s\n", __func__);
+
+ while (1) {
+ /* Select the chip if required */
+ if (cs_change)
+ zynqmp_qspi_chipselect(priv, 1);
+
+ cs_change = priv->cs_change;
+
+ if (!priv->tx_buf && !priv->rx_buf && priv->len) {
+ status = -1;
+ break;
+ }
+
+ /* Request the transfer */
+ if (priv->len) {
+ status = zynqmp_qspi_start_transfer(priv);
+ priv->is_inst = 0;
+ if (status < 0)
+ break;
+ }
+
+ if (cs_change)
+ /* Deselect the chip */
+ zynqmp_qspi_chipselect(priv, 0);
+ break;
+ }
+
+ return status;
+}
+
+static int zynqmp_qspi_claim_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+ struct zynqmp_qspi_regs *regs = priv->regs;
+
+ debug("%s\n", __func__);
+ writel(ZYNQMP_QSPI_ENABLE_ENABLE_MASK, ®s->enbr);
+
+ return 0;
+}
+
+static int zynqmp_qspi_release_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+ struct zynqmp_qspi_regs *regs = priv->regs;
+
+ debug("%s\n", __func__);
+ writel(~ZYNQMP_QSPI_ENABLE_ENABLE_MASK, ®s->enbr);
+
+ return 0;
+}
+
+int zynqmp_qspi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+
+ debug("%s: priv: 0x%08lx bitlen: %d dout: 0x%08lx ", __func__,
+ (unsigned long)priv, bitlen, (unsigned long)dout);
+ debug("din: 0x%08lx flags: 0x%lx\n", (unsigned long)din, flags);
+
+ priv->tx_buf = dout;
+ priv->rx_buf = din;
+ priv->len = bitlen / 8;
+
+ /*
+ * Festering sore.
+ * Assume that the beginning of a transfer with bits to
+ * transmit must contain a device command.
+ */
+ if (dout && flags & SPI_XFER_BEGIN)
+ priv->is_inst = 1;
+ else
+ priv->is_inst = 0;
+
+ if (flags & SPI_XFER_END)
+ priv->cs_change = 1;
+ else
+ priv->cs_change = 0;
+
+ if (flags & SPI_XFER_U_PAGE)
+ priv->u_page = 1;
+ else
+ priv->u_page = 0;
+
+ priv->stripe = 0;
+ priv->bus = 0;
+
+ if (priv->is_dual == SF_DUAL_PARALLEL_FLASH) {
+ if (flags & SPI_XFER_MASK)
+ priv->bus = (flags & SPI_XFER_MASK) >> 8;
+ if (flags & SPI_XFER_STRIPE)
+ priv->stripe = 1;
+ }
+
+ priv->dummy_bytes = slave->dummy_bytes;
+ zynqmp_qspi_transfer(priv);
+
+ return 0;
+}
+
+static const struct dm_spi_ops zynqmp_qspi_ops = {
+ .claim_bus = zynqmp_qspi_claim_bus,
+ .release_bus = zynqmp_qspi_release_bus,
+ .xfer = zynqmp_qspi_xfer,
+ .set_speed = zynqmp_qspi_set_speed,
+ .set_mode = zynqmp_qspi_set_mode,
+};
+
+static const struct udevice_id zynqmp_qspi_ids[] = {
+ { .compatible = "xlnx,zynqmp-qspi-1.0" },
+ { }
+};
+
+U_BOOT_DRIVER(zynqmp_qspi) = {
+ .name = "zynqmp_qspi",
+ .id = UCLASS_SPI,
+ .of_match = zynqmp_qspi_ids,
+ .ops = &zynqmp_qspi_ops,
+ .ofdata_to_platdata = zynqmp_qspi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct zynqmp_qspi_platdata),
+ .priv_auto_alloc_size = sizeof(struct zynqmp_qspi_priv),
+ .probe = zynqmp_qspi_probe,
+ .child_pre_probe = zynqmp_qspi_child_pre_probe,
+};
return USB_DR_MODE_UNKNOWN;
}
- error("usb maximum-speed not found\n");
+
+static const char *const speed_names[] = {
+ [USB_SPEED_UNKNOWN] = "UNKNOWN",
+ [USB_SPEED_LOW] = "low-speed",
+ [USB_SPEED_FULL] = "full-speed",
+ [USB_SPEED_HIGH] = "high-speed",
+ [USB_SPEED_WIRELESS] = "wireless",
+ [USB_SPEED_SUPER] = "super-speed",
+};
+
+enum usb_device_speed usb_get_maximum_speed(int node)
+{
+ const void *fdt = gd->fdt_blob;
+ const char *max_speed;
+ int i;
+
+ max_speed = fdt_getprop(fdt, node, "maximum-speed", NULL);
+ if (!max_speed) {
++ pr_err("usb maximum-speed not found\n");
+ return USB_SPEED_UNKNOWN;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(speed_names); i++)
+ if (!strcmp(max_speed, speed_names[i]))
+ return i;
+
+ return USB_SPEED_UNKNOWN;
+}
Say 'Y' here if you have one such device
+config USB_DWC3_GENERIC
+ bool "Xilinx ZynqMP and similar Platforms"
+ depends on DM_USB && USB_DWC3
+ help
+ Some platforms can reuse this DWC3 generic implementation.
+
+ config USB_DWC3_UNIPHIER
+ bool "DesignWare USB3 Host Support on UniPhier Platforms"
+ depends on ARCH_UNIPHIER && USB_XHCI_DWC3
+ help
+ Support of USB2/3 functionality in Socionext UniPhier platforms.
+ Say 'Y' here if you have one such device.
+
menu "PHY Subsystem"
config USB_DWC3_PHY_OMAP
obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o
obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
+obj-$(CONFIG_USB_DWC3_GENERIC) += dwc3-generic.o
+ obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o
obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o
obj-$(CONFIG_USB_DWC3_PHY_SAMSUNG) += samsung_usb_phy.o
--- /dev/null
- error("No USB device found\n");
+/**
+ * dwc3-generic.c - Generic DWC3 Glue layer
+ *
+ * Copyright (C) 2016 Xilinx, Inc.
+ *
+ * Based on dwc3-omap.c.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <linux/usb/otg.h>
+#include <linux/compat.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <malloc.h>
+#include <usb.h>
+#include "core.h"
+#include "gadget.h"
+#include "linux-compat.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int usb_gadget_handle_interrupts(int index)
+{
+ struct dwc3 *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_first_device(UCLASS_USB_DEV_GENERIC, &dev);
+ if (!dev || ret) {
- int node = dev->of_offset;
++ pr_err("No USB device found\n");
+ return -ENODEV;
+ }
+
+ priv = dev_get_priv(dev);
+
+ dwc3_gadget_uboot_handle_interrupt(priv);
+
+ return 0;
+}
+
+static int dwc3_generic_peripheral_probe(struct udevice *dev)
+{
+ struct dwc3 *priv = dev_get_priv(dev);
+
+ return dwc3_init(priv);
+}
+
+static int dwc3_generic_peripheral_remove(struct udevice *dev)
+{
+ struct dwc3 *priv = dev_get_priv(dev);
+
+ dwc3_remove(priv);
+
+ return 0;
+}
+
+static int dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev)
+{
+ struct dwc3 *priv = dev_get_priv(dev);
- priv->regs = (void *)dev_get_addr(dev);
++ int node = dev_of_offset(dev);
+
- error("Invalid usb maximum speed\n");
++ priv->regs = (void *)devfdt_get_addr(dev);
+ priv->regs += DWC3_GLOBALS_REGS_START;
+
+ priv->maximum_speed = usb_get_maximum_speed(node);
+ if (priv->maximum_speed == USB_SPEED_UNKNOWN) {
- error("Invalid usb mode setup\n");
++ pr_err("Invalid usb maximum speed\n");
+ return -ENODEV;
+ }
+
+ priv->dr_mode = usb_get_dr_mode(node);
+ if (priv->dr_mode == USB_DR_MODE_UNKNOWN) {
- for (node = fdt_first_subnode(fdt, parent->of_offset); node > 0;
++ pr_err("Invalid usb mode setup\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int dwc3_generic_peripheral_bind(struct udevice *dev)
+{
+ return device_probe(dev);
+}
+
+U_BOOT_DRIVER(dwc3_generic_peripheral) = {
+ .name = "dwc3-generic-peripheral",
+ .id = UCLASS_USB_DEV_GENERIC,
+ .ofdata_to_platdata = dwc3_generic_peripheral_ofdata_to_platdata,
+ .probe = dwc3_generic_peripheral_probe,
+ .remove = dwc3_generic_peripheral_remove,
+ .bind = dwc3_generic_peripheral_bind,
+ .platdata_auto_alloc_size = sizeof(struct usb_platdata),
+ .priv_auto_alloc_size = sizeof(struct dwc3),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+
+static int dwc3_generic_bind(struct udevice *parent)
+{
+ const void *fdt = gd->fdt_blob;
+ int node;
+ int ret;
+
- name, node, &dev);
++ for (node = fdt_first_subnode(fdt, dev_of_offset(parent)); node > 0;
+ node = fdt_next_subnode(fdt, node)) {
+ const char *name = fdt_get_name(fdt, node, NULL);
+ enum usb_dr_mode dr_mode;
+ struct udevice *dev;
+
+ debug("%s: subnode name: %s\n", __func__, name);
+ if (strncmp(name, "dwc3@", 4))
+ continue;
+
+ dr_mode = usb_get_dr_mode(node);
+
+ switch (dr_mode) {
+ case USB_DR_MODE_PERIPHERAL:
+ case USB_DR_MODE_OTG:
+ debug("%s: dr_mode: OTG or Peripheral\n", __func__);
+ ret = device_bind_driver_to_node(parent,
+ "dwc3-generic-peripheral",
- name, node, &dev);
++ name, offset_to_ofnode(node),
++ &dev);
+ if (ret) {
+ debug("%s: not able to bind usb device mode\n",
+ __func__);
+ return ret;
+ }
+ break;
+ case USB_DR_MODE_HOST:
+ debug("%s: dr_mode: HOST\n", __func__);
+ ret = device_bind_driver_to_node(parent,
+ "dwc3-generic-host",
++ name, offset_to_ofnode(node),
++ &dev);
+ if (ret) {
+ debug("%s: not able to bind usb host mode\n",
+ __func__);
+ return ret;
+ }
+ break;
+ default:
+ break;
+ };
+ }
+
+ return 0;
+}
+
+static const struct udevice_id dwc3_generic_ids[] = {
+ { .compatible = "xlnx,zynqmp-dwc3" },
+ { }
+};
+
+U_BOOT_DRIVER(dwc3_generic_wrapper) = {
+ .name = "dwc3-generic-wrapper",
+ .id = UCLASS_MISC,
+ .of_match = dwc3_generic_ids,
+ .bind = dwc3_generic_bind,
+};
return ret;
}
-int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+void xhci_hcd_stop(int index)
{
- struct zynqmp_xhci *ctx = &zynqmp_xhci;
- int ret = 0;
- uint32_t hclen;
+ /*
+ * Currently zynqmp socs do not support PHY shutdown from
+ * sw. But this support may be added in future socs.
+ */
- if (index < 0 || index >= ARRAY_SIZE(ctr_addr))
- return -EINVAL;
+ return;
+}
- ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
- ctx->dwc3_reg = (struct dwc3 *)((void *)ctx->hcd + DWC3_REG_OFFSET);
+static int xhci_usb_probe(struct udevice *dev)
+{
+ struct zynqmp_xhci_platdata *plat = dev_get_platdata(dev);
+ struct zynqmp_xhci *ctx = dev_get_priv(dev);
+ struct xhci_hcor *hcor;
+ int ret;
- ret = board_usb_init(index, USB_INIT_HOST);
- if (ret != 0) {
- puts("Failed to initialize board for USB\n");
- return ret;
- }
+ ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
+ ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
ret = zynqmp_xhci_core_init(ctx);
- if (ret < 0) {
- puts("Failed to initialize xhci\n");
- return ret;
+ if (ret) {
+ puts("XHCI: failed to initialize controller\n");
+ return -EINVAL;
}
- *hccr = (struct xhci_hccr *)ctx->hcd;
- hclen = HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase));
- *hcor = (struct xhci_hcor *)((uintptr_t) *hccr + hclen);
+ hcor = (struct xhci_hcor *)((ulong)ctx->hcd +
+ HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
- debug("zynqmp-xhci: init hccr %p and hcor %p hc_length %d\n",
- *hccr, *hcor, hclen);
- return ret;
+ return xhci_register(dev, ctx->hcd, hcor);
}
-void xhci_hcd_stop(int index)
+static int xhci_usb_remove(struct udevice *dev)
{
- /*
- * Currently zynqmp socs do not support PHY shutdown from
- * sw. But this support may be added in future socs.
- */
+ return xhci_deregister(dev);
+}
- return;
+static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct zynqmp_xhci_platdata *plat = dev_get_platdata(dev);
+ const void *blob = gd->fdt_blob;
+
+ /* Get the base address for XHCI controller from the device node */
- plat->hcd_base = fdtdec_get_addr(blob, dev->of_offset, "reg");
++ plat->hcd_base = fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
+ if (plat->hcd_base == FDT_ADDR_T_NONE) {
+ debug("Can't get the XHCI register base address\n");
+ return -ENXIO;
+ }
+
+ return 0;
}
+
+U_BOOT_DRIVER(dwc3_generic_host) = {
+ .name = "dwc3-generic-host",
+ .id = UCLASS_USB,
+ .ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
+ .probe = xhci_usb_probe,
+ .remove = xhci_usb_remove,
+ .ops = &xhci_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct zynqmp_xhci_platdata),
+ .priv_auto_alloc_size = sizeof(struct zynqmp_xhci),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
# define PARTS_DEFAULT
#endif
- #define CONFIG_BOARD_LATE_INIT
-
+/* Initial environment variables */
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr=0x80000\0" \
+ "initrd_addr=0xa00000\0" \
+ "initrd_size=0x2000000\0" \
+ "fdt_addr=4000000\0" \
+ "fdt_high=0x10000000\0" \
+ "loadbootenv_addr=0x100000\0" \
+ "sdbootdev=0\0"\
+ "kernel_offset=0x180000\0" \
+ "fdt_offset=0x100000\0" \
+ "kernel_size=0x1e00000\0" \
+ "fdt_size=0x80000\0" \
+ "bootenv=uEnv.txt\0" \
+ "bootargs=earlycon clk_ignore_unused\0" \
+ "loadbootenv=load mmc $sdbootdev:$partid ${loadbootenv_addr} ${bootenv}\0" \
+ "importbootenv=echo Importing environment from SD ...; " \
+ "env import -t ${loadbootenv_addr} $filesize\0" \
+ "sd_uEnvtxt_existence_test=test -e mmc $sdbootdev:$partid /uEnv.txt\0" \
+ "sata_root=if test $scsidevs -gt 0; then setenv bootargs $bootargs root=/dev/sda rw rootfstype=ext4; fi\0" \
+ "sataboot=load scsi 0 80000 boot/Image && load scsi 0 $fdt_addr boot/system.dtb && booti 80000 - $fdt_addr\0" \
+ "veloce=fdt addr f000000 && fdt resize" \
+ "fdt set /amba/misc_clk clock-frequency <48000> && "\
+ "fdt set /timer clock-frequency <240000> && " \
+ "fdt set /amba/i2c_clk clock-frequency <240000> && " \
+ "booti 80000 - f000000\0" \
+ "netboot=tftpboot 10000000 image.ub && bootm\0" \
+ "qspiboot=sf probe 0 0 0 && sf read $fdt_addr $fdt_offset $fdt_size && " \
+ "sf read $kernel_addr $kernel_offset $kernel_size && " \
+ "booti $kernel_addr - $fdt_addr\0" \
+ "uenvboot=" \
+ "if run sd_uEnvtxt_existence_test; then " \
+ "run loadbootenv; " \
+ "echo Loaded environment from ${bootenv}; " \
+ "run importbootenv; " \
+ "fi; " \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...; " \
+ "run uenvcmd; " \
+ "fi\0" \
+ "sdboot=mmc dev $sdbootdev && mmcinfo && run uenvboot || run sdroot$sdbootdev; " \
+ "load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \
+ "load mmc $sdbootdev:$partid $kernel_addr Image && " \
+ "booti $kernel_addr - $fdt_addr\0" \
+ "emmcboot=run sdboot\0" \
+ "nandboot=nand info && nand read $fdt_addr $fdt_offset $fdt_size && " \
+ "nand read $kernel_addr $kernel_offset $kernel_size && " \
+ "booti $kernel_addr - $fdt_addr\0" \
+ "xen_prepare_dt=fdt addr $fdt_addr && fdt resize 128 && " \
+ "fdt set /chosen \\\\#address-cells <1> && " \
+ "fdt set /chosen \\\\#size-cells <1> && " \
+ "fdt mknod /chosen dom0 && " \
+ "fdt set /chosen/dom0 compatible \"xen,linux-zimage\" \"xen,multiboot-module\" && " \
+ "fdt set /chosen/dom0 reg <0x80000 0x$filesize> && " \
+ "fdt set /chosen xen,xen-bootargs \"console=dtuart dtuart=serial0 dom0_mem=768M bootscrub=0 maxcpus=1 timer_slop=0\" && " \
+ "fdt set /chosen xen,dom0-bootargs \"console=hvc0 earlycon=xen earlyprintk=xen maxcpus=1 clk_ignore_unused\"\0" \
+ "xen_prepare_dt_qemu=run xen_prepare_dt && " \
+ "fdt set /cpus/cpu@1 device_type \"none\" && " \
+ "fdt set /cpus/cpu@2 device_type \"none\" && " \
+ "fdt set /cpus/cpu@3 device_type \"none\" && " \
+ "fdt rm /cpus/cpu@1 compatible && " \
+ "fdt rm /cpus/cpu@2 compatible && " \
+ "fdt rm /cpus/cpu@3 compatible\0" \
+ "xen=tftpb $fdt_addr system.dtb && tftpb 0x80000 Image &&" \
+ "run xen_prepare_dt && " \
+ "tftpb 6000000 xen.ub && tftpb 0x1000000 image.ub && " \
+ "bootm 6000000 0x1000000 $fdt_addr\0" \
+ "xen_qemu=tftpb $fdt_addr system.dtb && tftpb 0x80000 Image && " \
+ "run xen_prepare_dt_qemu && " \
+ "tftpb 6000000 xen.ub && tftpb 0x1000000 image.ub && " \
+ "bootm 6000000 0x1000000 $fdt_addr\0" \
+ "jtagboot=tftpboot 80000 Image && tftpboot $fdt_addr system.dtb && " \
+ "tftpboot 6000000 rootfs.cpio.ub && booti 80000 6000000 $fdt_addr\0" \
+ "nosmp=setenv bootargs $bootargs maxcpus=1\0" \
+ "nfsroot=setenv bootargs $bootargs root=/dev/nfs nfsroot=$serverip:/mnt/sata,tcp ip=$ipaddr:$serverip:$serverip:255.255.255.0:zynqmp:eth0:off rw\0" \
+ "sdroot0=setenv bootargs $bootargs root=/dev/mmcblk0p2 rw rootwait\0" \
+ "sdroot1=setenv bootargs $bootargs root=/dev/mmcblk1p2 rw rootwait\0" \
+ "android=setenv bootargs $bootargs init=/init androidboot.selinux=disabled androidboot.hardware=$board\0" \
+ "android_debug=run android && setenv bootargs $bootargs video=DP-1:1024x768@60 drm.debug=0xf\0" \
+ "usb_dfu_spl=booti $kernel_addr - $fdt_addr\0" \
+ "usbhostboot=usb start && load usb 0 $fdt_addr system.dtb && " \
+ "load usb 0 $kernel_addr Image && " \
+ "booti $kernel_addr - $fdt_addr\0" \
+ PARTS_DEFAULT \
+ DFU_ALT_INFO
+#endif
+
+#define CONFIG_PREBOOT "run setup"
+#define CONFIG_BOOTCOMMAND "run $modeboot"
+
/* Do not preserve environment */
- #if !defined(CONFIG_ENV_IS_IN_FAT)
- #define CONFIG_ENV_IS_NOWHERE 1
- #endif
#define CONFIG_ENV_SIZE 0x8000
/* Monitor Command Prompt */
--- /dev/null
- #define CONFIG_SYS_NO_FLASH
- #define _CONFIG_CMD_DEFAULT_H
+/*
+ * Configuration for Xilinx ZynqMP Flash utility
+ *
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ *
+ * Based on Configuration for Versatile Express
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_MINI_H
+#define __CONFIG_ZYNQMP_MINI_H
+
- #define CONFIG_FIT_DISABLE_SHA256
+/* #define CONFIG_SYS_DCACHE_OFF */
+#define CONFIG_SYS_ICACHE_OFF
- #undef CONFIG_ZYNQ_SERIAL
+
+#include <configs/xilinx_zynqmp.h>
+
+/* Undef unneeded configs */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOARD_LATE_INIT
+#undef CONFIG_BOOTCOMMAND
+#undef CONFIG_SYS_HUSH_PARSER
+#undef CONFIG_SYS_PROMPT_HUSH_PS2
+#undef CONFIG_PREBOOT
+#undef CONFIG_SYS_MALLOC_LEN
+#undef CONFIG_ENV_SIZE
+#undef CONFIG_CMDLINE_EDITING
+#undef CONFIG_AUTO_COMPLETE
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+#undef CONFIG_CMD_SPL
+#undef CONFIG_CMD_ENV
+#undef CONFIG_DOS_PARTITION
+#undef CONFIG_MP
+#undef CONFIG_SYS_INIT_SP_ADDR
+#undef CONFIG_SYS_LONGHELP
+#undef CONFIG_CMD_SF_TEST
+#undef CONFIG_FIT_VERBOSE
- # define CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_CMD_UBI
+#undef CONFIG_RBTREE
+#undef CONFIG_CMD_UBIFS
+#undef CONFIG_LZO
+#undef CONFIG_CMD_MTDPARTS
+#undef CONFIG_MTD_DEVICE
+#undef CONFIG_MTD_PARTITIONS
+#undef CONFIG_MTD_UBI_WL_THRESHOLD
+#undef CONFIG_MTD_UBI_BEB_LIMIT
+#undef CONFIG_SPI_FLASH_MTD
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_VXWORKS
+#undef CONFIG_BOOTM_LINUX
+#undef CONFIG_PARTITION_UUIDS
+#undef CONFIG_PARTITIONS
+#undef CONFIG_CMD_PART
+#undef CONFIG_CMD_CLK
+#undef CONFIG_ISO_PARTITION
+
+/* BOOTP options */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_BOOTPATH
+#undef CONFIG_BOOTP_GATEWAY
+#undef CONFIG_BOOTP_HOSTNAME
+#undef CONFIG_BOOTP_MAY_FAIL
+#undef CONFIG_BOOTP_PXE
+#undef CONFIG_CMD_UNZIP
+
+/* PXE */
+#undef CONFIG_CMD_PXE
+#undef CONFIG_MENU
+
+#undef CONFIG_NR_DRAM_BANKS
+#define CONFIG_NR_DRAM_BANKS 1
+
+#if defined(CONFIG_MINI_QSPI)
+# define CONFIG_SYS_SDRAM_SIZE (256 * 1024)
+# define CONFIG_SYS_SDRAM_BASE 0xFFFC0000
+# define CONFIG_ENV_SIZE 1400
+# define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x20000)
+# define CONFIG_SYS_MALLOC_LEN 0x2000
+# define CONFIG_MP
+
+#elif defined(CONFIG_MINI_NAND)
+# define CONFIG_SYS_SDRAM_SIZE 0x1000000
+# define CONFIG_SYS_SDRAM_BASE 0
+# define CONFIG_ENV_SIZE 0x10000
+# define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000)
+# define CONFIG_SYS_MALLOC_LEN 0x800000
+
+#elif defined(CONFIG_MINI_EMMC)
+# define CONFIG_ENV_SIZE 0x10000
+# define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+# define CONFIG_SYS_MALLOC_LEN 0x800000
+# define CONFIG_DOS_PARTITION
+# define CONFIG_PARTITIONS
+# define CONFIG_SYS_LONGHELP
+# undef CONFIG_ENV_IS_IN_FAT
+# undef FAT_ENV_DEVICE_AND_PART
+# undef FAT_ENV_FILE
+# undef FAT_ENV_INTERFACE
+#endif
+
+#endif /* __CONFIG_ZYNQMP_MINI_H */
#define CONFIG_SYS_I2C_ZYNQ
#define CONFIG_PCA953X
- #define CONFIG_CMD_PCA953X
- #define CONFIG_CMD_PCA953X_INFO
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
-
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
- #define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_EEPROM_BUS 5
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20
--- /dev/null
- #define CONFIG_CMD_PCA953X
- #define CONFIG_CMD_PCA953X_INFO
+/*
+ * Configuration for Xilinx ZynqMP zcu104
+ *
+ * (C) Copyright 2017 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZCU104_H
+#define __CONFIG_ZYNQMP_ZCU104_H
+
+#define CONFIG_ZYNQ_SDHCI1
+#define CONFIG_ZYNQ_I2C1
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_NUM_I2C_BUSES 9
+#define CONFIG_SYS_I2C_BUSES { \
+ {0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 5} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 6} } }, \
+ {0, {{I2C_MUX_PCA9548, 0x74, 7} } }, \
+ }
+
+#define CONFIG_SYS_I2C_ZYNQ
+#define CONFIG_PCA953X
- #define CONFIG_CMD_EEPROM
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZCU104_H */
--- /dev/null
- #define CONFIG_CMD_PCA953X
- #define CONFIG_CMD_PCA953X_INFO
+/*
+ * Configuration for Xilinx ZynqMP zcu106
+ *
+ * (C) Copyright 2016 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZCU106_H
+#define __CONFIG_ZYNQMP_ZCU106_H
+
+#define CONFIG_ZYNQ_SDHCI1
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_I2C1
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_NUM_I2C_BUSES 18
+#define CONFIG_SYS_I2C_BUSES { \
+ {0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \
+ {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \
+ {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \
+ {1, {I2C_NULL_HOP} }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
+ }
+
+#define CONFIG_SYS_I2C_ZYNQ
+#define CONFIG_PCA953X
- #define CONFIG_CMD_EEPROM
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_ZYNQ_EEPROM_BUS 5
+#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
+#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZCU106_H */
/* QSPI */
#ifdef CONFIG_ZYNQ_QSPI
# define CONFIG_SF_DEFAULT_SPEED 30000000
- # define CONFIG_SF_DUAL_FLASH
-# define CONFIG_SPI_FLASH_ISSI
#endif
/* NOR */
/* Environment */
#ifndef CONFIG_ENV_IS_NOWHERE
- # ifndef CONFIG_SYS_NO_FLASH
- /* Environment in NOR flash */
- # define CONFIG_ENV_IS_IN_FLASH
- # elif defined(CONFIG_ZYNQ_QSPI)
- /* Environment in Serial Flash */
- # define CONFIG_ENV_IS_IN_SPI_FLASH
- # elif defined(CONFIG_NAND_ZYNQ)
- /* Environment in NAND flash */
- # define CONFIG_ENV_IS_IN_NAND
- # elif defined(CONFIG_SYS_NO_FLASH)
- # define CONFIG_ENV_IS_NOWHERE
- # endif
-
# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# define CONFIG_ENV_OFFSET 0xE0000
+
+/* cc108 requires to be 0xF00000 to have boot.bin with bitstream included */
+# ifndef CONFIG_ENV_OFFSET
+# define CONFIG_ENV_OFFSET 0xE0000
+# endif
#endif
/* enable preboot to be loaded before CONFIG_BOOTDELAY */
#define CONFIG_PREBOOT
+ /* Boot configuration */
++/* default boot is according to the bootmode switch settings */
++#if defined(CONFIG_CMD_ZYNQ_RSA)
++#define CONFIG_BOOTCOMMAND "run rsa_$modeboot || run distro_bootcmd"
++#else
+ #define CONFIG_BOOTCOMMAND "run $modeboot || run distro_bootcmd"
++#endif
+ #define CONFIG_SYS_LOAD_ADDR 0 /* default? */
+
+ /* Distro boot enablement */
+
+ #ifdef CONFIG_SPL_BUILD
+ #define BOOTENV
+ #else
+ #include <config_distro_defaults.h>
+
+ #ifdef CONFIG_CMD_MMC
+ #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+ #else
+ #define BOOT_TARGET_DEVICES_MMC(func)
+ #endif
+
+ #ifdef CONFIG_CMD_USB
+ #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+ #else
+ #define BOOT_TARGET_DEVICES_USB(func)
+ #endif
+
+ #if defined(CONFIG_CMD_PXE)
+ #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
+ #else
+ #define BOOT_TARGET_DEVICES_PXE(func)
+ #endif
+
+ #if defined(CONFIG_CMD_DHCP)
+ #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
+ #else
+ #define BOOT_TARGET_DEVICES_DHCP(func)
+ #endif
+
+ #define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_DEVICES_MMC(func) \
+ BOOT_TARGET_DEVICES_USB(func) \
+ BOOT_TARGET_DEVICES_PXE(func) \
+ BOOT_TARGET_DEVICES_DHCP(func)
+
+ #include <config_distro_bootcmd.h>
+ #endif /* CONFIG_SPL_BUILD */
+
/* Default environment */
#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
- "fit_image=fit.itb\0" \
- "load_addr=0x2000000\0" \
- "fit_size=0x800000\0" \
- "flash_off=0x100000\0" \
- "nor_flash_off=0xE2100000\0" \
- "fdt_high=0x20000000\0" \
- "initrd_high=0x20000000\0" \
+ "ethaddr=00:0a:35:00:01:22\0" \
+ "kernel_image=uImage\0" \
+ "kernel_load_address=0x2080000\0" \
+ "ramdisk_image=uramdisk.image.gz\0" \
+ "ramdisk_load_address=0x4000000\0" \
+ "devicetree_image=devicetree.dtb\0" \
+ "devicetree_load_address=0x2000000\0" \
+ "bitstream_image=system.bit.bin\0" \
+ "boot_image=BOOT.bin\0" \
+ "loadbit_addr=0x100000\0" \
"loadbootenv_addr=0x2000000\0" \
- "fdt_addr_r=0x1f00000\0" \
- "pxefile_addr_r=0x2000000\0" \
- "kernel_addr_r=0x2000000\0" \
- "scriptaddr=0x3000000\0" \
- "ramdisk_addr_r=0x3100000\0" \
+ "kernel_size=0x500000\0" \
+ "devicetree_size=0x20000\0" \
+ "ramdisk_size=0x5E0000\0" \
+ "boot_size=0xF00000\0" \
+ "fdt_high=0x20000000\0" \
+ "initrd_high=0x20000000\0" \
"bootenv=uEnv.txt\0" \
- "bootenv_dev=mmc\0" \
- "loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \
- "importbootenv=echo Importing environment from ${bootenv_dev} ...; " \
+ "loadbootenv=load mmc 0 ${loadbootenv_addr} ${bootenv}\0" \
+ "importbootenv=echo Importing environment from SD ...; " \
"env import -t ${loadbootenv_addr} $filesize\0" \
- "bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \
- "setbootenv=if env run bootenv_existence_test; then " \
- "if env run loadbootenv; then " \
- "env run importbootenv; " \
- "fi; " \
- "fi; \0" \
- "sd_loadbootenv=set bootenv_dev mmc && " \
- "run setbootenv \0" \
- "usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv \0" \
- "preboot=if test $modeboot = sdboot; then " \
- "run sd_loadbootenv; " \
- "echo Checking if uenvcmd is set ...; " \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...; " \
- "run uenvcmd; " \
+ "sd_uEnvtxt_existence_test=test -e mmc 0 /uEnv.txt\0" \
+ "preboot=if test $modeboot = sdboot && env run sd_uEnvtxt_existence_test; " \
+ "then if env run loadbootenv; " \
+ "then env run importbootenv; " \
"fi; " \
"fi; \0" \
- "norboot=echo Copying FIT from NOR flash to RAM... && " \
- "cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \
- "bootm ${load_addr}\0" \
- "sdboot=echo Copying FIT from SD to RAM... && " \
- "load mmc 0 ${load_addr} ${fit_image} && " \
- "bootm ${load_addr}\0" \
- "jtagboot=echo TFTPing FIT to RAM... && " \
- "tftpboot ${load_addr} ${fit_image} && " \
- "bootm ${load_addr}\0" \
+ "mmc_loadbit=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
+ "mmcinfo && " \
+ "load mmc 0 ${loadbit_addr} ${bitstream_image} && " \
+ "fpga load 0 ${loadbit_addr} ${filesize}\0" \
+ "norboot=echo Copying Linux from NOR flash to RAM... && " \
+ "cp.b 0xE2100000 ${kernel_load_address} ${kernel_size} && " \
+ "cp.b 0xE2600000 ${devicetree_load_address} ${devicetree_size} && " \
+ "echo Copying ramdisk... && " \
+ "cp.b 0xE2620000 ${ramdisk_load_address} ${ramdisk_size} && " \
+ "bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}\0" \
+ "qspiboot=echo Copying Linux from QSPI flash to RAM... && " \
+ "sf probe 0 0 0 && " \
+ "sf read ${kernel_load_address} 0x100000 ${kernel_size} && " \
+ "sf read ${devicetree_load_address} 0x600000 ${devicetree_size} && " \
+ "echo Copying ramdisk... && " \
+ "sf read ${ramdisk_load_address} 0x620000 ${ramdisk_size} && " \
+ "bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}\0" \
+ "uenvboot=" \
+ "if run loadbootenv; then " \
+ "echo Loaded environment from ${bootenv}; " \
+ "run importbootenv; " \
+ "fi; " \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...; " \
+ "run uenvcmd; " \
+ "fi\0" \
+ "sdboot=if mmcinfo; then " \
+ "run uenvboot; " \
+ "echo Copying Linux from SD to RAM... && " \
+ "load mmc 0 ${kernel_load_address} ${kernel_image} && " \
+ "load mmc 0 ${devicetree_load_address} ${devicetree_image} && " \
+ "load mmc 0 ${ramdisk_load_address} ${ramdisk_image} && " \
+ "bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}; " \
+ "fi\0" \
"usbboot=if usb start; then " \
- "echo Copying FIT from USB to RAM... && " \
- "load usb 0 ${load_addr} ${fit_image} && " \
- "bootm ${load_addr}; fi\0" \
+ "run uenvboot; " \
+ "echo Copying Linux from USB to RAM... && " \
+ "load usb 0 ${kernel_load_address} ${kernel_image} && " \
+ "load usb 0 ${devicetree_load_address} ${devicetree_image} && " \
+ "load usb 0 ${ramdisk_load_address} ${ramdisk_image} && " \
+ "bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}; " \
+ "fi\0" \
+ "nandboot=echo Copying Linux from NAND flash to RAM... && " \
+ "nand read ${kernel_load_address} 0x100000 ${kernel_size} && " \
+ "nand read ${devicetree_load_address} 0x600000 ${devicetree_size} && " \
+ "echo Copying ramdisk... && " \
+ "nand read ${ramdisk_load_address} 0x620000 ${ramdisk_size} && " \
+ "bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}\0" \
+ "jtagboot=echo TFTPing Linux to RAM... && " \
+ "tftpboot ${kernel_load_address} ${kernel_image} && " \
+ "tftpboot ${devicetree_load_address} ${devicetree_image} && " \
+ "tftpboot ${ramdisk_load_address} ${ramdisk_image} && " \
+ "bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}\0" \
+ "rsa_norboot=echo Copying Image from NOR flash to RAM... && " \
+ "cp.b 0xE2100000 0x100000 ${boot_size} && " \
+ "zynqrsa 0x100000 && " \
+ "bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}\0" \
+ "rsa_nandboot=echo Copying Image from NAND flash to RAM... && " \
+ "nand read 0x100000 0x0 ${boot_size} && " \
+ "zynqrsa 0x100000 && " \
+ "bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}\0" \
+ "rsa_qspiboot=echo Copying Image from QSPI flash to RAM... && " \
+ "sf probe 0 0 0 && " \
+ "sf read 0x100000 0x0 ${boot_size} && " \
+ "zynqrsa 0x100000 && " \
+ "bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}\0" \
+ "rsa_sdboot=echo Copying Image from SD to RAM... && " \
+ "load mmc 0 0x100000 ${boot_image} && " \
+ "zynqrsa 0x100000 && " \
+ "bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}\0" \
+ "rsa_jtagboot=echo TFTPing Image to RAM... && " \
+ "tftpboot 0x100000 ${boot_image} && " \
+ "zynqrsa 0x100000 && " \
+ "bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}\0" \
- DFU_ALT_INFO
+ DFU_ALT_INFO \
+ BOOTENV
#endif
- /* default boot is according to the bootmode switch settings */
- #if defined(CONFIG_CMD_ZYNQ_RSA)
- #define CONFIG_BOOTCOMMAND "run rsa_$modeboot"
- #else
- #define CONFIG_BOOTCOMMAND "run $modeboot"
- #endif
- #define CONFIG_SYS_LOAD_ADDR 0 /* default? */
-
/* Miscellaneous configurable options */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
- #define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_LONGHELP
#define CONFIG_CLOCKS
- #define CONFIG_CMD_CLK
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
+#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
#ifndef CONFIG_NR_DRAM_BANKS
# define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_LDSCRIPT "arch/arm/mach-zynq/u-boot.lds"
--/* Commands */
- #if defined(CONFIG_CMD_ZYNQ_RSA)
- #define CONFIG_SHA256
- #endif
-
+#undef CONFIG_BOOTM_NETBSD
+
+#define CONFIG_SYS_HZ 1000
+
+/* For development/debugging */
+#ifdef DEBUG
+# define CONFIG_CMD_REGINFO
+# define CONFIG_PANIC_HANG
+#endif
/* SPL part */
- #define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
- #define CONFIG_SPL_BOARD_INIT
- #define CONFIG_SPL_RAM_DEVICE
-
- #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-zynq/u-boot-spl.lds"
+/* FPGA support */
+#define CONFIG_SPL_FPGA_SUPPORT
+#define CONFIG_SPL_FPGA_LOAD_ADDR 0x1000000
+/* #define CONFIG_SPL_FPGA_BIT */
+#ifdef CONFIG_SPL_FPGA_BIT
+# define CONFIG_SPL_FPGA_LOAD_ARGS_NAME "download.bit"
+#else
+# define CONFIG_SPL_FPGA_LOAD_ARGS_NAME "fpga.bin"
+#endif
+
/* MMC support */
- #ifdef CONFIG_ZYNQ_SDHCI
+ #ifdef CONFIG_MMC_SDHCI_ZYNQ
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
#define CONFIG_SPL_BSS_START_ADDR 0x20000
#define CONFIG_SPL_BSS_MAX_SIZE 0x8000
-#define CONFIG_SYS_SDRAM_BASE 0xfffc0000
-#define CONFIG_SYS_SDRAM_SIZE 0x40000
-
+ #undef CONFIG_SYS_MALLOC_LEN
+ #define CONFIG_SYS_MALLOC_LEN 0x1000
+
#endif /* __CONFIG_ZYNQ_CSE_H */
char init_in_progress; /* 1 if we have done mmc_start_init() */
char preinit; /* start init as early as possible */
int ddr_mode;
- #ifdef CONFIG_DM_MMC
+ #if CONFIG_IS_ENABLED(DM_MMC)
struct udevice *dev; /* Device for this MMC controller */
#endif
+ u8 is_uhs;
+ u8 uhsmode;
+ u8 forcehs;
};
struct mmc_hwpart_conf {
#define SDHCI_BUFFER 0x20
#define SDHCI_PRESENT_STATE 0x24
- #define SDHCI_CMD_INHIBIT 0x00000001
- #define SDHCI_DATA_INHIBIT 0x00000002
- #define SDHCI_DOING_WRITE 0x00000100
- #define SDHCI_DOING_READ 0x00000200
- #define SDHCI_SPACE_AVAILABLE 0x00000400
- #define SDHCI_DATA_AVAILABLE 0x00000800
- #define SDHCI_CARD_PRESENT 0x00010000
- #define SDHCI_CARD_STATE_STABLE 0x00020000
- #define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000
- #define SDHCI_WRITE_PROTECT 0x00080000
+ #define SDHCI_CMD_INHIBIT BIT(0)
+ #define SDHCI_DATA_INHIBIT BIT(1)
+ #define SDHCI_DOING_WRITE BIT(8)
+ #define SDHCI_DOING_READ BIT(9)
+ #define SDHCI_SPACE_AVAILABLE BIT(10)
+ #define SDHCI_DATA_AVAILABLE BIT(11)
+ #define SDHCI_CARD_PRESENT BIT(16)
+ #define SDHCI_CARD_STATE_STABLE BIT(17)
+ #define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
+ #define SDHCI_WRITE_PROTECT BIT(19)
+#define SDHCI_DATA_BUSY 0xF00000
+#define SDHCI_CMD_BUSY 0x1000000
#define SDHCI_HOST_CONTROL 0x28
- #define SDHCI_CTRL_LED 0x01
- #define SDHCI_CTRL_4BITBUS 0x02
- #define SDHCI_CTRL_HISPD 0x04
+ #define SDHCI_CTRL_LED BIT(0)
+ #define SDHCI_CTRL_4BITBUS BIT(1)
+ #define SDHCI_CTRL_HISPD BIT(2)
#define SDHCI_CTRL_DMA_MASK 0x18
#define SDHCI_CTRL_SDMA 0x00
#define SDHCI_CTRL_ADMA1 0x08
#define SDHCI_CLOCK_BASE_SHIFT 8
#define SDHCI_MAX_BLOCK_MASK 0x00030000
#define SDHCI_MAX_BLOCK_SHIFT 16
- #define SDHCI_CAN_DO_8BIT 0x00040000
- #define SDHCI_CAN_DO_ADMA2 0x00080000
- #define SDHCI_CAN_DO_ADMA1 0x00100000
- #define SDHCI_CAN_DO_HISPD 0x00200000
- #define SDHCI_CAN_DO_SDMA 0x00400000
- #define SDHCI_CAN_VDD_330 0x01000000
- #define SDHCI_CAN_VDD_300 0x02000000
- #define SDHCI_CAN_VDD_180 0x04000000
- #define SDHCI_CAN_64BIT 0x10000000
+ #define SDHCI_CAN_DO_8BIT BIT(18)
+ #define SDHCI_CAN_DO_ADMA2 BIT(19)
+ #define SDHCI_CAN_DO_ADMA1 BIT(20)
+ #define SDHCI_CAN_DO_HISPD BIT(21)
+ #define SDHCI_CAN_DO_SDMA BIT(22)
+ #define SDHCI_CAN_VDD_330 BIT(24)
+ #define SDHCI_CAN_VDD_300 BIT(25)
+ #define SDHCI_CAN_VDD_180 BIT(26)
+ #define SDHCI_CAN_64BIT BIT(28)
#define SDHCI_CAPABILITIES_1 0x44
+#define SDHCI_SUPPORT_SDR50 0x00000001
+#define SDHCI_SUPPORT_SDR104 0x00000002
+#define SDHCI_SUPPORT_DDR50 0x00000004
+#define SDHCI_USE_SDR50_TUNING 0x00002000
+#define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
+
#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
#define SDHCI_CLOCK_MUL_SHIFT 16
#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
- #define SDHCI_QUIRK_NO_CD (1 << 5)
#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
- #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 7)
#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
+#define SDHCI_QUIRK_NO_1_8_V (1 << 9)
+#define SDHCI_QUIRK_USE_ACMD12 (1 << 10)
/* to make gcc happy */
struct sdhci_host;
}
gd->ram_size = (phys_size_t)(res.end - res.start + 1);
- debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+ gd->ram_top = (unsigned long)res.start;
+ debug("%s: Initial DRAM size %llx\n", __func__,
+ (unsigned long long)gd->ram_size);
return 0;
}
CONFIG_ZLT
CONFIG_ZM7300
CONFIG_ZYNQMP_EEPROM
--CONFIG_ZYNQMP_XHCI_LIST
CONFIG_ZYNQ_EEPROM
CONFIG_ZYNQ_EEPROM_BUS
CONFIG_ZYNQ_GEM_EEPROM_ADDR
projects / thirdparty / u-boot.git / commitdiff
