;; -----------------------------------------------------------------------------
(define_split
- [(set (match_operand:VB 0 "register_operand")
- (if_then_else:VB
- (unspec:VB
- [(match_operand:VB 1 "vector_all_trues_mask_operand")
+ [(set (match_operand:VB_VLS 0 "register_operand")
+ (if_then_else:VB_VLS
+ (unspec:VB_VLS
+ [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand")
(match_operand 4 "vector_length_operand")
(match_operand 5 "const_int_operand")
(match_operand 6 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operand:VB 3 "vector_move_operand")
- (match_operand:VB 2 "vector_undef_operand")))]
+ (match_operand:VB_VLS 3 "vector_move_operand")
+ (match_operand:VB_VLS 2 "vector_undef_operand")))]
"TARGET_VECTOR"
[(const_int 0)]
{
;; Combine neg + vfsgnj to vfsgnjn
(define_insn_and_split "*copysign<mode>_neg"
- [(set (match_operand:VF 0 "register_operand")
- (neg:VF
- (unspec:VF [
- (match_operand:VF 1 "register_operand")
- (match_operand:VF 2 "register_operand")
+ [(set (match_operand:V_VLSF 0 "register_operand")
+ (neg:V_VLSF
+ (unspec:V_VLSF [
+ (match_operand:V_VLSF 1 "register_operand")
+ (match_operand:V_VLSF 2 "register_operand")
] UNSPEC_VCOPYSIGN)))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
;; =========================================================================
(define_expand "mask_len_load<mode><vm>"
- [(match_operand:V 0 "register_operand")
- (match_operand:V 1 "memory_operand")
+ [(match_operand:V_VLS 0 "register_operand")
+ (match_operand:V_VLS 1 "memory_operand")
(match_operand:<VM> 2 "vector_mask_operand")
- (match_operand:V 3 "maskload_else_operand")
+ (match_operand:V_VLS 3 "maskload_else_operand")
(match_operand 4 "autovec_length_operand")
(match_operand 5 "const_0_operand")]
"TARGET_VECTOR"
})
(define_expand "mask_len_store<mode><vm>"
- [(match_operand:V 0 "memory_operand")
- (match_operand:V 1 "register_operand")
+ [(match_operand:V_VLS 0 "memory_operand")
+ (match_operand:V_VLS 1 "register_operand")
(match_operand:<VM> 2 "vector_mask_operand")
(match_operand 3 "autovec_length_operand")
(match_operand 4 "const_0_operand")]
;; Slide an RVV vector left and insert a scalar into element 0.
(define_expand "vec_shl_insert_<mode>"
- [(match_operand:VI 0 "register_operand")
- (match_operand:VI 1 "register_operand")
+ [(match_operand:V_VLSI 0 "register_operand")
+ (match_operand:V_VLSI 1 "register_operand")
(match_operand:<VEL> 2 "reg_or_0_operand")]
"TARGET_VECTOR"
{
})
(define_expand "vec_shl_insert_<mode>"
- [(match_operand:VF 0 "register_operand")
- (match_operand:VF 1 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
+ (match_operand:V_VLSF 1 "register_operand")
(match_operand:<VEL> 2 "register_operand")]
"TARGET_VECTOR"
{
)
(define_expand "vcond_mask_len_<mode>"
- [(match_operand:V 0 "register_operand")
+ [(match_operand:V_VLS 0 "register_operand")
(match_operand:<VM> 1 "nonmemory_operand")
- (match_operand:V 2 "nonmemory_operand")
- (match_operand:V 3 "autovec_else_operand")
+ (match_operand:V_VLS 2 "nonmemory_operand")
+ (match_operand:V_VLS 3 "autovec_else_operand")
(match_operand 4 "autovec_length_operand")
(match_operand 5 "const_0_operand")]
"TARGET_VECTOR"
})
(define_expand "cond_len_<optab><mode>"
- [(match_operand:VI 0 "register_operand")
+ [(match_operand:V_VLSI 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (any_int_unop:VI
- (match_operand:VI 2 "register_operand"))
- (match_operand:VI 3 "autovec_else_operand")
+ (any_int_unop:V_VLSI
+ (match_operand:V_VLSI 2 "register_operand"))
+ (match_operand:V_VLSI 3 "autovec_else_operand")
(match_operand 4 "autovec_length_operand")
(match_operand 5 "const_0_operand")]
"TARGET_VECTOR"
})
(define_expand "cond_len_<optab><mode>"
- [(match_operand:VF 0 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (any_float_unop_nofrm:VF
- (match_operand:VF 2 "register_operand"))
- (match_operand:VF 3 "autovec_else_operand")
+ (any_float_unop_nofrm:V_VLSF
+ (match_operand:V_VLSF 2 "register_operand"))
+ (match_operand:V_VLSF 3 "autovec_else_operand")
(match_operand 4 "autovec_length_operand")
(match_operand 5 "const_0_operand")]
"TARGET_VECTOR"
})
(define_expand "cond_len_<optab><mode>"
- [(match_operand:VI 0 "register_operand")
+ [(match_operand:V_VLSI 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (any_shift:VI
- (match_operand:VI 2 "register_operand")
- (match_operand:VI 3 "vector_shift_operand"))
- (match_operand:VI 4 "autovec_else_operand")
+ (any_shift:V_VLSI
+ (match_operand:V_VLSI 2 "register_operand")
+ (match_operand:V_VLSI 3 "vector_shift_operand"))
+ (match_operand:V_VLSI 4 "autovec_else_operand")
(match_operand 5 "autovec_length_operand")
(match_operand 6 "const_0_operand")]
"TARGET_VECTOR"
})
(define_expand "cond_len_<optab><mode>"
- [(match_operand:VI 0 "register_operand")
+ [(match_operand:V_VLSI 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (any_int_binop_no_shift:VI
- (match_operand:VI 2 "<binop_rhs1_predicate>")
- (match_operand:VI 3 "<binop_rhs2_predicate>"))
- (match_operand:VI 4 "autovec_else_operand")
+ (any_int_binop_no_shift:V_VLSI
+ (match_operand:V_VLSI 2 "<binop_rhs1_predicate>")
+ (match_operand:V_VLSI 3 "<binop_rhs2_predicate>"))
+ (match_operand:V_VLSI 4 "autovec_else_operand")
(match_operand 5 "autovec_length_operand")
(match_operand 6 "const_0_operand")]
"TARGET_VECTOR"
})
(define_expand "cond_len_<optab><mode>"
- [(match_operand:VF 0 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (any_float_binop:VF
- (match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand"))
- (match_operand:VF 4 "autovec_else_operand")
+ (any_float_binop:V_VLSF
+ (match_operand:V_VLSF 2 "register_operand")
+ (match_operand:V_VLSF 3 "register_operand"))
+ (match_operand:V_VLSF 4 "autovec_else_operand")
(match_operand 5 "autovec_length_operand")
(match_operand 6 "const_0_operand")]
"TARGET_VECTOR"
})
(define_expand "cond_len_<optab><mode>"
- [(match_operand:VF 0 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (any_float_binop_nofrm:VF
- (match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand"))
- (match_operand:VF 4 "autovec_else_operand")
+ (any_float_binop_nofrm:V_VLSF
+ (match_operand:V_VLSF 2 "register_operand")
+ (match_operand:V_VLSF 3 "register_operand"))
+ (match_operand:V_VLSF 4 "autovec_else_operand")
(match_operand 5 "autovec_length_operand")
(match_operand 6 "const_0_operand")]
"TARGET_VECTOR"
})
(define_expand "cond_len_<ieee_fmaxmin_op><mode>"
- [(match_operand:VF 0 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (unspec:VF
- [(match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand")] UNSPEC_VFMAXMIN)
- (match_operand:VF 4 "autovec_else_operand")
+ (unspec:V_VLSF
+ [(match_operand:V_VLSF 2 "register_operand")
+ (match_operand:V_VLSF 3 "register_operand")] UNSPEC_VFMAXMIN)
+ (match_operand:V_VLSF 4 "autovec_else_operand")
(match_operand 5 "autovec_length_operand")
(match_operand 6 "const_0_operand")]
"TARGET_VECTOR && !HONOR_SNANS (<MODE>mode)"
})
(define_expand "cond_len_fma<mode>"
- [(match_operand:VI 0 "register_operand")
+ [(match_operand:V_VLSI 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand:VI 2 "register_operand")
- (match_operand:VI 3 "register_operand")
- (match_operand:VI 4 "register_operand")
- (match_operand:VI 5 "autovec_else_operand")
+ (match_operand:V_VLSI 2 "register_operand")
+ (match_operand:V_VLSI 3 "register_operand")
+ (match_operand:V_VLSI 4 "register_operand")
+ (match_operand:V_VLSI 5 "autovec_else_operand")
(match_operand 6 "autovec_length_operand")
(match_operand 7 "const_0_operand")]
"TARGET_VECTOR"
})
(define_expand "cond_len_fnma<mode>"
- [(match_operand:VI 0 "register_operand")
+ [(match_operand:V_VLSI 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand:VI 2 "register_operand")
- (match_operand:VI 3 "register_operand")
- (match_operand:VI 4 "register_operand")
- (match_operand:VI 5 "autovec_else_operand")
+ (match_operand:V_VLSI 2 "register_operand")
+ (match_operand:V_VLSI 3 "register_operand")
+ (match_operand:V_VLSI 4 "register_operand")
+ (match_operand:V_VLSI 5 "autovec_else_operand")
(match_operand 6 "autovec_length_operand")
(match_operand 7 "const_0_operand")]
"TARGET_VECTOR"
})
(define_expand "cond_len_fma<mode>"
- [(match_operand:VF 0 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand")
- (match_operand:VF 4 "register_operand")
- (match_operand:VF 5 "autovec_else_operand")
+ (match_operand:V_VLSF 2 "register_operand")
+ (match_operand:V_VLSF 3 "register_operand")
+ (match_operand:V_VLSF 4 "register_operand")
+ (match_operand:V_VLSF 5 "autovec_else_operand")
(match_operand 6 "autovec_length_operand")
(match_operand 7 "const_0_operand")]
"TARGET_VECTOR"
})
(define_expand "cond_len_fnma<mode>"
- [(match_operand:VF 0 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand")
- (match_operand:VF 4 "register_operand")
- (match_operand:VF 5 "autovec_else_operand")
+ (match_operand:V_VLSF 2 "register_operand")
+ (match_operand:V_VLSF 3 "register_operand")
+ (match_operand:V_VLSF 4 "register_operand")
+ (match_operand:V_VLSF 5 "autovec_else_operand")
(match_operand 6 "autovec_length_operand")
(match_operand 7 "const_0_operand")]
"TARGET_VECTOR"
})
(define_expand "cond_len_fms<mode>"
- [(match_operand:VF 0 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand")
- (match_operand:VF 4 "register_operand")
- (match_operand:VF 5 "autovec_else_operand")
+ (match_operand:V_VLSF 2 "register_operand")
+ (match_operand:V_VLSF 3 "register_operand")
+ (match_operand:V_VLSF 4 "register_operand")
+ (match_operand:V_VLSF 5 "autovec_else_operand")
(match_operand 6 "autovec_length_operand")
(match_operand 7 "const_0_operand")]
"TARGET_VECTOR"
})
(define_expand "cond_len_fnms<mode>"
- [(match_operand:VF 0 "register_operand")
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand")
- (match_operand:VF 4 "register_operand")
- (match_operand:VF 5 "autovec_else_operand")
+ (match_operand:V_VLSF 2 "register_operand")
+ (match_operand:V_VLSF 3 "register_operand")
+ (match_operand:V_VLSF 4 "register_operand")
+ (match_operand:V_VLSF 5 "autovec_else_operand")
(match_operand 6 "autovec_length_operand")
(match_operand 7 "const_0_operand")]
"TARGET_VECTOR"
(define_insn_and_split "mask_len_fold_left_plus_<mode>"
[(set (match_operand:<VEL> 0 "register_operand")
(unspec:<VEL> [
- (match_operand:VF 2 "register_operand")
+ (match_operand:V_VLSF 2 "register_operand")
(match_operand:<VEL> 1 "register_operand")
(match_operand:<VM> 3 "vector_mask_operand")
(match_operand 4 "autovec_length_operand")
;; - vfmv.f.s
;; -------------------------------------------------------------------------
+;; If this is available for VLS modes we sometimes don't fall back to
+;; non-partial accesses, thus missing a vectorization opportunity.
+;; See PR122938.
(define_expand "len_fold_extract_last_<mode>"
[(match_operand:<VEL> 0 "register_operand")
(match_operand:<VEL> 1 "register_operand")
;; - vrol.vv vror.vv
;; -------------------------------------------------------------------------
(define_expand "v<bitmanip_optab><mode>3"
- [(set (match_operand:VI 0 "register_operand")
- (bitmanip_rotate:VI
- (match_operand:VI 1 "register_operand")
- (match_operand:VI 2 "register_operand")))]
+ [(set (match_operand:V_VLSI 0 "register_operand")
+ (bitmanip_rotate:V_VLSI
+ (match_operand:V_VLSI 1 "register_operand")
+ (match_operand:V_VLSI 2 "register_operand")))]
"TARGET_ZVBB || TARGET_ZVKB"
{
riscv_vector::emit_vlmax_insn (code_for_pred_v (<CODE>, <MODE>mode),
(set_attr "mode" "<MODE>")])
(define_insn "@pred_v<bitmanip_optab><mode>"
- [(set (match_operand:VI 0 "register_operand" "=vd,vd, vr, vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" " rK,rK, rK, rK")
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (bitmanip_rotate:VI
- (match_operand:VI 3 "register_operand" " vr,vr, vr, vr")
- (match_operand:VI 4 "register_operand" " vr,vr, vr, vr"))
- (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ (bitmanip_rotate:V_VLSI
+ (match_operand:V_VLSI 3 "register_operand" " vr,vr, vr, vr")
+ (match_operand:V_VLSI 4 "register_operand" " vr,vr, vr, vr"))
+ (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_ZVBB || TARGET_ZVKB"
"v<bitmanip_insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "v<bitmanip_insn>")
(set_attr "mode" "<MODE>")])
(define_insn "@pred_v<bitmanip_optab><mode>_scalar"
- [(set (match_operand:VI 0 "register_operand" "=vd,vd, vr, vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" " rK,rK, rK, rK")
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (bitmanip_rotate:VI
- (match_operand:VI 3 "register_operand" " vr,vr, vr, vr")
+ (bitmanip_rotate:V_VLSI
+ (match_operand:V_VLSI 3 "register_operand" " vr,vr, vr, vr")
(match_operand 4 "pmode_register_operand" " r, r, r, r"))
- (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_ZVBB || TARGET_ZVKB"
"v<bitmanip_insn>.vx\t%0,%3,%4%p1"
[(set_attr "type" "v<bitmanip_insn>")
(set_attr "mode" "<MODE>")])
(define_insn "*pred_vror<mode>_scalar"
- [(set (match_operand:VI 0 "register_operand" "=vd,vd, vr,vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr,vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" " rK,rK, rK, rK")
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (rotatert:VI
- (match_operand:VI 3 "register_operand" " vr,vr, vr, vr")
+ (rotatert:V_VLSI
+ (match_operand:V_VLSI 3 "register_operand" " vr,vr, vr, vr")
(match_operand 4 "const_csr_operand" " K, K, K, K"))
- (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_ZVBB || TARGET_ZVKB"
"vror.vi\t%0,%3,%4%p1"
[(set_attr "type" "vror")
;; vclmul.vv vclmul.vx
;; vclmulh.vv vclmulh.vx
(define_insn "@pred_vclmul<h><mode>"
- [(set (match_operand:VI_D 0 "register_operand" "=vd,vr,vd, vr")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vr,vd, vr")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,Wc1,vm,Wc1")
(match_operand 5 "vector_length_operand" "rK, rK,rK, rK")
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:VI_D
- [(match_operand:VI_D 3 "register_operand" "vr, vr,vr, vr")
- (match_operand:VI_D 4 "register_operand" "vr, vr,vr, vr")] UNSPEC_CLMUL_VC)
- (match_operand:VI_D 2 "vector_merge_operand" "vu, vu, 0, 0")))]
+ (unspec:V_VLSI_D
+ [(match_operand:V_VLSI_D 3 "register_operand" "vr, vr,vr, vr")
+ (match_operand:V_VLSI_D 4 "register_operand" "vr, vr,vr, vr")] UNSPEC_CLMUL_VC)
+ (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, vu, 0, 0")))]
"TARGET_ZVBC"
"vclmul<h>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vclmul<h>")
;; Deal with SEW = 64 in RV32 system.
(define_expand "@pred_vclmul<h><mode>_scalar"
- [(set (match_operand:VI_D 0 "register_operand")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand")
(match_operand 5 "vector_length_operand")
(match_operand 8 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:VI_D
- [(vec_duplicate:VI_D
+ (unspec:V_VLSI_D
+ [(vec_duplicate:V_VLSI_D
(match_operand:<VEL> 4 "register_operand"))
- (match_operand:VI_D 3 "register_operand")] UNSPEC_CLMUL_VC)
- (match_operand:VI_D 2 "vector_merge_operand")))]
+ (match_operand:V_VLSI_D 3 "register_operand")] UNSPEC_CLMUL_VC)
+ (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
"TARGET_ZVBC"
{
if (riscv_vector::sew64_scalar_helper (
})
(define_insn "*pred_vclmul<h><mode>_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd,vr,vd, vr")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vr,vd, vr")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,Wc1,vm,Wc1")
(match_operand 5 "vector_length_operand" "rK, rK,rK, rK")
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:VI_D
- [(vec_duplicate:VI_D
+ (unspec:V_VLSI_D
+ [(vec_duplicate:V_VLSI_D
(match_operand:<VEL> 4 "reg_or_0_operand" "rJ, rJ,rJ, rJ"))
- (match_operand:VI_D 3 "register_operand" "vr, vr,vr, vr")] UNSPEC_CLMUL_VC)
- (match_operand:VI_D 2 "vector_merge_operand" "vu, vu, 0, 0")))]
+ (match_operand:V_VLSI_D 3 "register_operand" "vr, vr,vr, vr")] UNSPEC_CLMUL_VC)
+ (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, vu, 0, 0")))]
"TARGET_ZVBC"
"vclmul<h>.vx\t%0,%3,%4%p1"
[(set_attr "type" "vclmul<h>")
(set_attr "mode" "<MODE>")])
(define_insn "*pred_vclmul<h><mode>_extend_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd,vr,vd, vr")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vr,vd, vr")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,Wc1,vm,Wc1")
(match_operand 5 "vector_length_operand" "rK, rK,rK, rK")
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:VI_D
- [(vec_duplicate:VI_D
+ (unspec:V_VLSI_D
+ [(vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
(match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ,rJ, rJ")))
- (match_operand:VI_D 3 "register_operand" "vr, vr,vr, vr")] UNSPEC_CLMUL_VC)
- (match_operand:VI_D 2 "vector_merge_operand" "vu, vu, 0, 0")))]
+ (match_operand:V_VLSI_D 3 "register_operand" "vr, vr,vr, vr")] UNSPEC_CLMUL_VC)
+ (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, vu, 0, 0")))]
"TARGET_ZVBC"
"vclmul<h>.vx\t%0,%3,%4%p1"
[(set_attr "type" "vclmul<h>")
;; vaesef.[vv,vs] vaesem.[vv,vs] vaesdf.[vv,vs] vaesdm.[vv,vs]
;; vsm4r.[vv,vs]
(define_insn "@pred_crypto_vv<vv_ins_name><ins_type><mode>"
- [(set (match_operand:VSI 0 "register_operand" "=vr")
- (if_then_else:VSI
+ [(set (match_operand:V_VLSI_S 0 "register_operand" "=vr")
+ (if_then_else:V_VLSI_S
(unspec:<VM>
[(match_operand 3 "vector_length_operand" " rK")
(match_operand 4 "const_int_operand" " i")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:VSI
- [(match_operand:VSI 1 "register_operand" " 0")
- (match_operand:VSI 2 "register_operand" "vr")] UNSPEC_CRYPTO_VV)
+ (unspec:V_VLSI_S
+ [(match_operand:V_VLSI_S 1 "register_operand" " 0")
+ (match_operand:V_VLSI_S 2 "register_operand" "vr")] UNSPEC_CRYPTO_VV)
(match_dup 1)))]
"TARGET_ZVKNED || TARGET_ZVKSED || TARGET_ZVKG"
"v<vv_ins_name>.<ins_type>\t%0,%2"
(set_attr "mode" "<MODE>")])
(define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x1<mode>_scalar"
- [(set (match_operand:VSI 0 "register_operand" "=&vr")
- (if_then_else:VSI
+ [(set (match_operand:V_VLSI_S 0 "register_operand" "=&vr")
+ (if_then_else:V_VLSI_S
(unspec:<VM>
[(match_operand 3 "vector_length_operand" " rK")
(match_operand 4 "const_int_operand" " i")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:VSI
- [(match_operand:VSI 1 "register_operand" " 0")
- (match_operand:VSI 2 "register_operand" "vr")] UNSPEC_CRYPTO_VV)
+ (unspec:V_VLSI_S
+ [(match_operand:V_VLSI_S 1 "register_operand" " 0")
+ (match_operand:V_VLSI_S 2 "register_operand" "vr")] UNSPEC_CRYPTO_VV)
(match_dup 1)))]
"TARGET_ZVKNED || TARGET_ZVKSED"
"v<vv_ins_name>.<ins_type>\t%0,%2"
(set_attr "mode" "<MODE>")])
(define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x2<mode>_scalar"
- [(set (match_operand:<VSIX2> 0 "register_operand" "=&vr")
- (if_then_else:<VSIX2>
+ [(set (match_operand:<V_VLSI_S_X2> 0 "register_operand" "=&vr")
+ (if_then_else:<V_VLSI_S_X2>
(unspec:<VM>
[(match_operand 3 "vector_length_operand" "rK")
(match_operand 4 "const_int_operand" " i")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:<VSIX2>
- [(match_operand:<VSIX2> 1 "register_operand" " 0")
- (match_operand:VLMULX2_SI 2 "register_operand" "vr")] UNSPEC_CRYPTO_VV)
+ (unspec:<V_VLSI_S_X2>
+ [(match_operand:<V_VLSI_S_X2> 1 "register_operand" " 0")
+ (match_operand:V_VLSI_S_LMULX2 2 "register_operand" "vr")] UNSPEC_CRYPTO_VV)
(match_dup 1)))]
"TARGET_ZVKNED || TARGET_ZVKSED"
"v<vv_ins_name>.<ins_type>\t%0,%2"
(set_attr "mode" "<MODE>")])
(define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x4<mode>_scalar"
- [(set (match_operand:<VSIX4> 0 "register_operand" "=&vr")
- (if_then_else:<VSIX4>
+ [(set (match_operand:<V_VLSI_S_X4> 0 "register_operand" "=&vr")
+ (if_then_else:<V_VLSI_S_X4>
(unspec:<VM>
[(match_operand 3 "vector_length_operand" " rK")
(match_operand 4 "const_int_operand" " i")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:<VSIX4>
- [(match_operand:<VSIX4> 1 "register_operand" " 0")
- (match_operand:VLMULX4_SI 2 "register_operand" "vr")] UNSPEC_CRYPTO_VV)
+ (unspec:<V_VLSI_S_X4>
+ [(match_operand:<V_VLSI_S_X4> 1 "register_operand" " 0")
+ (match_operand:V_VLSI_S_LMULX4 2 "register_operand" "vr")] UNSPEC_CRYPTO_VV)
(match_dup 1)))]
"TARGET_ZVKNED || TARGET_ZVKSED"
"v<vv_ins_name>.<ins_type>\t%0,%2"
(set_attr "mode" "<MODE>")])
(define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x8<mode>_scalar"
- [(set (match_operand:<VSIX8> 0 "register_operand" "=&vr")
- (if_then_else:<VSIX8>
+ [(set (match_operand:<V_VLSI_S_X8> 0 "register_operand" "=&vr")
+ (if_then_else:<V_VLSI_S_X8>
(unspec:<VM>
[(match_operand 3 "vector_length_operand" " rK")
(match_operand 4 "const_int_operand" " i")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:<VSIX8>
- [(match_operand:<VSIX8> 1 "register_operand" " 0")
- (match_operand:VLMULX8_SI 2 "register_operand" " vr")] UNSPEC_CRYPTO_VV)
+ (unspec:<V_VLSI_S_X8>
+ [(match_operand:<V_VLSI_S_X8> 1 "register_operand" " 0")
+ (match_operand:V_VLSI_S_LMULX8 2 "register_operand" " vr")] UNSPEC_CRYPTO_VV)
(match_dup 1)))]
"TARGET_ZVKNED || TARGET_ZVKSED"
"v<vv_ins_name>.<ins_type>\t%0,%2"
(set_attr "mode" "<MODE>")])
(define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x16<mode>_scalar"
- [(set (match_operand:<VSIX16> 0 "register_operand" "=&vr")
- (if_then_else:<VSIX16>
+ [(set (match_operand:<V_VLSI_S_X16> 0 "register_operand" "=&vr")
+ (if_then_else:<V_VLSI_S_X16>
(unspec:<VM>
[(match_operand 3 "vector_length_operand" " rK")
(match_operand 4 "const_int_operand" " i")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:<VSIX16>
- [(match_operand:<VSIX16> 1 "register_operand" " 0")
- (match_operand:VLMULX16_SI 2 "register_operand" " vr")] UNSPEC_CRYPTO_VV)
+ (unspec:<V_VLSI_S_X16>
+ [(match_operand:<V_VLSI_S_X16> 1 "register_operand" " 0")
+ (match_operand:V_VLSI_S_LMULX16 2 "register_operand" " vr")] UNSPEC_CRYPTO_VV)
(match_dup 1)))]
"TARGET_ZVKNED || TARGET_ZVKSED"
"v<vv_ins_name>.<ins_type>\t%0,%2"
;; vaeskf1.vi vsm4k.vi
(define_insn "@pred_crypto_vi<vi_ins_name><mode>_scalar"
- [(set (match_operand:VSI 0 "register_operand" "=vr, vr")
- (if_then_else:VSI
+ [(set (match_operand:V_VLSI_S 0 "register_operand" "=vr, vr")
+ (if_then_else:V_VLSI_S
(unspec:<VM>
[(match_operand 4 "vector_length_operand" "rK, rK")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:VSI
- [(match_operand:VSI 2 "register_operand" "vr, vr")
+ (unspec:V_VLSI_S
+ [(match_operand:V_VLSI_S 2 "register_operand" "vr, vr")
(match_operand 3 "const_int_operand" " i, i")] UNSPEC_CRYPTO_VI)
- (match_operand:VSI 1 "vector_merge_operand" "vu, 0")))]
+ (match_operand:V_VLSI_S 1 "vector_merge_operand" "vu, 0")))]
"TARGET_ZVKNED || TARGET_ZVKSED"
"v<vi_ins_name>.vi\t%0,%2,%3"
[(set_attr "type" "v<vi_ins_name>")
;; vaeskf2.vi vsm3c.vi
(define_insn "@pred_vi<vi_ins1_name><mode>_nomaskedoff_scalar"
- [(set (match_operand:VSI 0 "register_operand" "=vr")
- (if_then_else:VSI
+ [(set (match_operand:V_VLSI_S 0 "register_operand" "=vr")
+ (if_then_else:V_VLSI_S
(unspec:<VM>
[(match_operand 4 "vector_length_operand" "rK")
(match_operand 5 "const_int_operand" " i")
(match_operand 6 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:VSI
- [(match_operand:VSI 1 "register_operand" " 0")
- (match_operand:VSI 2 "register_operand" "vr")
+ (unspec:V_VLSI_S
+ [(match_operand:V_VLSI_S 1 "register_operand" " 0")
+ (match_operand:V_VLSI_S 2 "register_operand" "vr")
(match_operand 3 "const_int_operand" " i")] UNSPEC_CRYPTO_VI1)
(match_dup 1)))]
"TARGET_ZVKNED || TARGET_ZVKSH"
;; zvksh instructions patterns.
;; vsm3me.vv
(define_insn "@pred_vsm3me<mode>"
- [(set (match_operand:VSI 0 "register_operand" "=vr, vr")
- (if_then_else:VSI
+ [(set (match_operand:V_VLSI_S 0 "register_operand" "=vr, vr")
+ (if_then_else:V_VLSI_S
(unspec:<VM>
[(match_operand 4 "vector_length_operand" " rK, rK")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:VSI
- [(match_operand:VSI 2 "register_operand" " vr, vr")
- (match_operand:VSI 3 "register_operand" " vr, vr")] UNSPEC_VSM3ME)
- (match_operand:VSI 1 "vector_merge_operand" " vu, 0")))]
+ (unspec:V_VLSI_S
+ [(match_operand:V_VLSI_S 2 "register_operand" " vr, vr")
+ (match_operand:V_VLSI_S 3 "register_operand" " vr, vr")] UNSPEC_VSM3ME)
+ (match_operand:V_VLSI_S 1 "vector_merge_operand" " vu, 0")))]
"TARGET_ZVKSH"
"vsm3me.vv\t%0,%2,%3"
[(set_attr "type" "vsm3me")
RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_VECTOR_ELEN_64")
RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_VECTOR_ELEN_64")
+
+ (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)")
+ (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)")
+ (V4QI "riscv_vector::vls_mode_valid_p (V4QImode)")
+ (V8QI "riscv_vector::vls_mode_valid_p (V8QImode)")
+ (V16QI "riscv_vector::vls_mode_valid_p (V16QImode)")
+ (V32QI "riscv_vector::vls_mode_valid_p (V32QImode)")
+ (V64QI "riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= 64")
+ (V128QI "riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= 128")
+ (V256QI "riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= 256")
+ (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= 512")
+ (V1024QI "riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN >= 1024")
+ (V2048QI "riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN >= 2048")
+ (V4096QI "riscv_vector::vls_mode_valid_p (V4096QImode) && TARGET_MIN_VLEN >= 4096")
+ (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)")
+ (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)")
+ (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)")
+ (V8HI "riscv_vector::vls_mode_valid_p (V8HImode)")
+ (V16HI "riscv_vector::vls_mode_valid_p (V16HImode)")
+ (V32HI "riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= 64")
+ (V64HI "riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= 128")
+ (V128HI "riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= 256")
+ (V256HI "riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= 512")
+ (V512HI "riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= 1024")
+ (V1024HI "riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN >= 2048")
+ (V2048HI "riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN >= 4096")
])
(define_mode_iterator VI_QHS [
(V2048BI "riscv_vector::vls_mode_valid_p (V2048BImode) && TARGET_MIN_VLEN >= 2048")
(V4096BI "riscv_vector::vls_mode_valid_p (V4096BImode) && TARGET_MIN_VLEN >= 4096")])
-(define_mode_iterator VSI [
+(define_mode_iterator V_VLSI_S [
RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_VECTOR_ELEN_64")
+
+ (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
+ (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
+ (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
+ (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
+ (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64")
+ (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128")
+ (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256")
+ (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512")
+ (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024")
+ (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048")
+ (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN >= 4096")
])
-(define_mode_iterator VLMULX2_SI [
+(define_mode_iterator V_VLSI_S_LMULX2 [
RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_VECTOR_ELEN_64")
+
+ (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
+ (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
+ (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
+ (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
+ (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64")
+ (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128")
+ (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256")
+ (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512")
+ (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024")
+ (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048")
])
-(define_mode_iterator VLMULX4_SI [
+(define_mode_iterator V_VLSI_S_LMULX4 [
RVVM2SI RVVM1SI (RVVMF2SI "TARGET_VECTOR_ELEN_64")
+
+ (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
+ (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
+ (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
+ (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
+ (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64")
+ (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128")
+ (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256")
+ (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512")
+ (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024")
])
-(define_mode_iterator VLMULX8_SI [
+(define_mode_iterator V_VLSI_S_LMULX8 [
RVVM1SI (RVVMF2SI "TARGET_VECTOR_ELEN_64")
+
+ (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
+ (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
+ (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
+ (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
+ (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64")
+ (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128")
+ (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256")
+ (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512")
])
-(define_mode_iterator VLMULX16_SI [
+(define_mode_iterator V_VLSI_S_LMULX16 [
(RVVMF2SI "TARGET_VECTOR_ELEN_64")
+
+ (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
+ (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
+ (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
+ (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
+ (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64")
+ (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128")
+ (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256")
])
-(define_mode_attr VSIX2 [
- (RVVM8SI "RVVM8SI") (RVVM4SI "RVVM8SI") (RVVM2SI "RVVM4SI") (RVVM1SI "RVVM2SI") (RVVMF2SI "RVVM1SI")
+(define_mode_attr V_VLSI_S_X2 [
+ (RVVM4SI "RVVM8SI") (RVVM2SI "RVVM4SI") (RVVM1SI "RVVM2SI") (RVVMF2SI "RVVM1SI")
+
+ (V1SI "V2SI")
+ (V2SI "V4SI")
+ (V4SI "V8SI")
+ (V8SI "V16SI")
+ (V16SI "V32SI")
+ (V32SI "V64SI")
+ (V64SI "V128SI")
+ (V128SI "V256SI")
+ (V256SI "V512SI")
+ (V512SI "V1024SI")
])
-(define_mode_attr VSIX4 [
+(define_mode_attr V_VLSI_S_X4 [
(RVVM2SI "RVVM8SI") (RVVM1SI "RVVM4SI") (RVVMF2SI "RVVM2SI")
+
+ (V1SI "V4SI")
+ (V2SI "V8SI")
+ (V4SI "V16SI")
+ (V8SI "V32SI")
+ (V16SI "V64SI")
+ (V32SI "V128SI")
+ (V64SI "V256SI")
+ (V128SI "V512SI")
+ (V256SI "V1024SI")
])
-(define_mode_attr VSIX8 [
+(define_mode_attr V_VLSI_S_X8 [
(RVVM1SI "RVVM8SI") (RVVMF2SI "RVVM4SI")
+
+ (V1SI "V8SI")
+ (V2SI "V16SI")
+ (V4SI "V32SI")
+ (V8SI "V64SI")
+ (V16SI "V128SI")
+ (V32SI "V256SI")
+ (V64SI "V512SI")
+ (V128SI "V1024SI")
])
-(define_mode_attr VSIX16 [
+(define_mode_attr V_VLSI_S_X16 [
(RVVMF2SI "RVVM8SI")
+
+ (V1SI "V16SI")
+ (V2SI "V32SI")
+ (V4SI "V64SI")
+ (V8SI "V128SI")
+ (V16SI "V256SI")
+ (V32SI "V512SI")
+ (V64SI "V1024SI")
])
(define_mode_iterator VLS_HAS_HALF [
;; -----------------------------------------------------------------
(define_insn "@vundefined<mode>"
- [(set (match_operand:V 0 "register_operand" "=vr")
- (unspec:V [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
+ [(set (match_operand:V_VLS 0 "register_operand" "=vr")
+ (unspec:V_VLS [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
"TARGET_VECTOR"
""
[(set_attr "type" "vector")])
(define_insn "@vundefined<mode>"
- [(set (match_operand:VB 0 "register_operand" "=vr")
- (unspec:VB [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
+ [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
+ (unspec:VB_VLS [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
"TARGET_VECTOR"
""
[(set_attr "type" "vector")])
[(set_attr "type" "vector")])
(define_expand "@vreinterpret<mode>"
- [(set (match_operand:V 0 "register_operand")
+ [(set (match_operand:V_VLS 0 "register_operand")
(match_operand 1 "vector_any_register_operand"))]
"TARGET_VECTOR"
{
;; Dedicated pattern for vse.v instruction since we can't reuse pred_mov pattern to include
;; memory operand as input which will produce inferior codegen.
(define_insn "@pred_store<mode>"
- [(set (match_operand:V 0 "memory_operand" "+m")
- (if_then_else:V
+ [(set (match_operand:V_VLS 0 "memory_operand" "+m")
+ (if_then_else:V_VLS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
(match_operand 3 "vector_length_operand" " rvl")
(match_operand 4 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operand:V 2 "register_operand" " vr")
+ (match_operand:V_VLS 2 "register_operand" " vr")
(match_dup 0)))]
"TARGET_VECTOR"
"vse<sew>.v\t%2,%0%p1"
[(set_attr "type" "vmpop")
(set_attr "mode" "<VB_VLS:MODE>")])
-(define_insn "@pred_ffs<VB:mode><P:mode>"
+(define_insn "@pred_ffs<VB
_VLS:mode><P:mode>"
[(set (match_operand:P 0 "register_operand" "=r")
(plus:P
(ffs:P
- (unspec:VB
- [(and:VB
- (match_operand:VB 1 "vector_mask_operand" "vmWc1")
- (match_operand:VB 2 "register_operand" " vr"))
+ (unspec:VB_VLS
+ [(and:VB_VLS
+ (match_operand:VB_VLS 1 "vector_mask_operand" "vmWc1")
+ (match_operand:VB_VLS 2 "register_operand" " vr"))
(match_operand 3 "vector_length_operand" " rvl")
(match_operand 4 "const_int_operand" " i")
(reg:SI VL_REGNUM)
"TARGET_VECTOR"
"vfirst.m\t%0,%2%p1"
[(set_attr "type" "vmffs")
- (set_attr "mode" "<VB:MODE>")])
+ (set_attr "mode" "<VB_VLS:MODE>")])
(define_insn "@pred_<misc_op><mode>"
- [(set (match_operand:VB 0 "register_operand" "=&vr, &vr")
- (if_then_else:VB
- (unspec:VB
- [(match_operand:VB 1 "vector_mask_operand" "vmWc1,vmWc1")
+ [(set (match_operand:VB_VLS 0 "register_operand" "=&vr, &vr")
+ (if_then_else:VB_VLS
+ (unspec:VB_VLS
+ [(match_operand:VB_VLS 1 "vector_mask_operand" "vmWc1,vmWc1")
(match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:VB
- [(match_operand:VB 3 "register_operand" " vr, vr")] VMISC)
- (match_operand:VB 2 "vector_merge_operand" " vu, 0")))]
+ (unspec:VB_VLS
+ [(match_operand:VB_VLS 3 "register_operand" " vr, vr")] VMISC)
+ (match_operand:VB_VLS 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"vm<misc_op>.m\t%0,%3%p1"
[(set_attr "type" "vmsfs")
(set_attr "mode" "<MODE>")])
(define_insn "@pred_iota<mode>"
- [(set (match_operand:VI 0 "register_operand" "=&vr, &vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=&vr, &vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
(match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:VI
+ (unspec:V_VLSI
[(match_operand:<VM> 3 "register_operand" " vr, vr")] UNSPEC_VIOTA)
- (match_operand:VI 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"viota.m\t%0,%3%p1"
[(set_attr "type" "vmiota")
(set_attr "mode" "<MODE>")])
(define_insn "@pred_ncopysign<mode>"
- [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
+ (if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (neg:VF
- (unspec:VF
- [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
- (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN))
- (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ (neg:V_VLSF
+ (unspec:V_VLSF
+ [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
+ (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN))
+ (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfsgnjn.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfsgnj")
(set_attr "mode" "<MODE>")])
(define_insn "@pred_ncopysign<mode>_scalar"
- [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
+ (if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (neg:VF
- (unspec:VF
- [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
- (vec_duplicate:VF
+ (neg:V_VLSF
+ (unspec:V_VLSF
+ [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
+ (vec_duplicate:V_VLSF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] UNSPEC_VCOPYSIGN))
- (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfsgnjn.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfsgnj")
(set (attr "avl_type_idx") (const_int 7))])
(define_insn "@pred_<misc_op><mode>"
- [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
+ (if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 7 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:VF
- [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
- (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ (unspec:V_VLSF
+ [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
+ (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vf<misc_op>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
(define_insn "@pred_<misc_frm_op><mode>"
- [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
+ (if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:VF
- [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC_FRM)
- (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ (unspec:V_VLSF
+ [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")] VFMISC_FRM)
+ (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vf<misc_frm_op>.v\t%0,%3%p1"
[(set_attr "type" "<float_frm_insn_type>")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(unspec:<VCONVERT>
- [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
+ [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfclass.v\t%0,%3%p1"
(set_attr "mode" "DI")])
(define_insn "@pred_fault_load<mode>"
- [(set (match_operand:V 0 "register_operand" "=vd, vd, vr, vr")
- (if_then_else:V
+ [(set (match_operand:V_VLS 0 "register_operand" "=vd, vd, vr, vr")
+ (if_then_else:V_VLS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, Wc1, Wc1")
(match_operand 4 "vector_length_operand" " rvl, rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:V
- [(match_operand:V 3 "memory_operand" " m, m, m, m")] UNSPEC_VLEFF)
- (match_operand:V 2 "vector_merge_operand" " vu, 0, vu, 0")))
+ (unspec:V_VLS
+ [(match_operand:V_VLS 3 "memory_operand" " m, m, m, m")] UNSPEC_VLEFF)
+ (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0, vu, 0")))
(set (reg:SI VL_REGNUM)
(unspec:SI
- [(if_then_else:V
+ [(if_then_else:V_VLS
(unspec:<VM>
[(match_dup 1) (match_dup 4) (match_dup 5)
(match_dup 6) (match_dup 7)
(reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:V [(match_dup 3)] UNSPEC_VLEFF)
+ (unspec:V_VLS [(match_dup 3)] UNSPEC_VLEFF)
(match_dup 2))] UNSPEC_MODIFY_VL))]
"TARGET_VECTOR"
"vle<sew>ff.v\t%0,%3%p1"
TEST_ALL (TEST_LOOP)
-/* { dg-final { scan-tree-dump-times " \.MASK_LEN_STRIDED_STORE " 44 "optimized" } } */
+/* { dg-final { scan-tree-dump-times " \.MASK_LEN_STRIDED_STORE " 44 "optimized" { target { no-opts "-mrvv-max-lmul=dynamic" "-mrvv-max-lmul=m8" } } } } */
+/* { dg-final { scan-tree-dump-times " \.MASK_LEN_STRIDED_STORE " 49 "optimized" { target { any-opts "-mrvv-max-lmul=dynamic" "-mrvv-max-lmul=m8" } } } } */
/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "optimized" } } */
/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "optimized" } } */
}
/* { dg-final { scan-tree-dump "Choosing vector mode V4QI" "vect" } } */
-/* { dg-final { scan-tree-dump "Choosing epilogue vector mode RVVM1SI" "vect" } } */
+/* { dg-final { scan-tree-dump "operating on partial vectors." "vect" } } */
/*
** foo:
-** vsetivli\t[a-x0-9]+,\s*8,\s*e(8?|16?|32?|64),\s*m(1?|2?|4?|8?|f2?|f4?|f8),\s*t[au],\s*m[au]
+** vsetivli\tzero,\s*4,\s*e(8?|16?|32?|64),\s*m(1?|2?|4?|8?|f2?|f4?|f8),\s*t[au],\s*m[au]
** ...
** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
** ...
-** vsetvli\tzero,\s*[a-x0-9]+,\s*e(8?|16?|32?|64),\s*m(1?|2?|4?|8?|f2?|f4?|f8),\s*t[au],\s*m[au]
-** ...
** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
** ...
*/
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 6 "vect" } } */
+/* With length-control for VLS modes we don't vectorize foo4 anymore.
+ That's due to a very tight costing decision in the small loop.
+ Therefore expect 5 instead of 6 vectorized loops. */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */
+/* Same as in zve64d-1.c we don't vectorize foo4 anymore due to an
+ unfortunately tight costing decision. Therefore expect 4 instead of 5
+ vectorized loops. */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
projects / thirdparty / gcc.git / commitdiff
