dt-bindings: cache: l2c2x0: Add missing power-domains

On Renesas SH-Mobile and R-Mobile SoCs, the ARM PL310 L2 Cache
Controller is located in a controllable power area.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/0a57ab356e5f426e28ead373b809f88a63e55380.1781105151.git.geert+renesas@glider.be
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>

diff --git a/Documentation/devicetree/bindings/cache/l2c2x0.yaml b/Documentation/devicetree/bindings/cache/l2c2x0.yaml
index 10c1a900202fc2ed7496f34c676f77ee5d7a4402..ee604117ffb3fe745e8f097eda6400cc66ede7d3 100644 (file)
--- a/Documentation/devicetree/bindings/cache/l2c2x0.yaml
+++ b/Documentation/devicetree/bindings/cache/l2c2x0.yaml
@@ -66,6 +66,9 @@ properties:
   reg:
     maxItems: 1
 
+  power-domains:
+    maxItems: 1
+
   arm,data-latency:
     description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
       read, write and setup latencies. Minimum valid values are 1. Controllers