drm/amd/pm: Update dpm table structs for smu_v15_0

Update dpm table structs to use common definitions for smu_15_0

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h
index 06842d38c92bdd494455c3697bdf1cf15d0be330..3c8c086f0f9d8085117a3cb8451c9ad8f51e0be8 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h
@@ -45,7 +45,6 @@
 
 #define FEATURE_MASK(feature) (1ULL << feature)
 
-#define MAX_DPM_LEVELS 16
 #define MAX_PCIE_CONF 3
 
 #define SMU15_TOOL_SIZE                        0x19000
@@ -69,39 +68,19 @@ struct smu_15_0_max_sustainable_clocks {
        uint32_t soc_clock;
 };
 
-struct smu_15_0_dpm_clk_level {
-       bool                            enabled;
-       uint32_t                        value;
-};
-
-struct smu_15_0_dpm_table {
-       uint32_t                        min;        /* MHz */
-       uint32_t                        max;        /* MHz */
-       uint32_t                        count;
-       bool                            is_fine_grained;
-       struct smu_15_0_dpm_clk_level   dpm_levels[MAX_DPM_LEVELS];
-};
-
-struct smu_15_0_pcie_table {
-       uint8_t  pcie_gen[MAX_PCIE_CONF];
-       uint8_t  pcie_lane[MAX_PCIE_CONF];
-       uint16_t clk_freq[MAX_PCIE_CONF];
-       uint32_t num_of_link_levels;
-};
-
 struct smu_15_0_dpm_tables {
-       struct smu_15_0_dpm_table        soc_table;
-       struct smu_15_0_dpm_table        gfx_table;
-       struct smu_15_0_dpm_table        uclk_table;
-       struct smu_15_0_dpm_table        eclk_table;
-       struct smu_15_0_dpm_table        vclk_table;
-       struct smu_15_0_dpm_table        dclk_table;
-       struct smu_15_0_dpm_table        dcef_table;
-       struct smu_15_0_dpm_table        pixel_table;
-       struct smu_15_0_dpm_table        display_table;
-       struct smu_15_0_dpm_table        phy_table;
-       struct smu_15_0_dpm_table        fclk_table;
-       struct smu_15_0_pcie_table       pcie_table;
+       struct smu_dpm_table        soc_table;
+       struct smu_dpm_table        gfx_table;
+       struct smu_dpm_table        uclk_table;
+       struct smu_dpm_table        eclk_table;
+       struct smu_dpm_table        vclk_table;
+       struct smu_dpm_table        dclk_table;
+       struct smu_dpm_table        dcef_table;
+       struct smu_dpm_table        pixel_table;
+       struct smu_dpm_table        display_table;
+       struct smu_dpm_table        phy_table;
+       struct smu_dpm_table        fclk_table;
+       struct smu_pcie_table       pcie_table;
 };
 
 struct smu_15_0_dpm_context {
@@ -204,7 +183,7 @@ int smu_v15_0_set_power_source(struct smu_context *smu,
 
 int smu_v15_0_set_single_dpm_table(struct smu_context *smu,
                                   enum smu_clk_type clk_type,
-                                  struct smu_15_0_dpm_table *single_dpm_table);
+                                  struct smu_dpm_table *single_dpm_table);
 
 int smu_v15_0_gfx_ulv_control(struct smu_context *smu,
                              bool enablement);

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
index 21df9705fda9ab761aac17eb0da6163ca732a663..eb3fa767c848aae60371c1c7d3a52415c3168553 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
@@ -1058,18 +1058,12 @@ int smu_v15_0_set_performance_level(struct smu_context *smu,
 {
        struct smu_15_0_dpm_context *dpm_context =
                smu->smu_dpm.dpm_context;
-       struct smu_15_0_dpm_table *gfx_table =
-               &dpm_context->dpm_tables.gfx_table;
-       struct smu_15_0_dpm_table *mem_table =
-               &dpm_context->dpm_tables.uclk_table;
-       struct smu_15_0_dpm_table *soc_table =
-               &dpm_context->dpm_tables.soc_table;
-       struct smu_15_0_dpm_table *vclk_table =
-               &dpm_context->dpm_tables.vclk_table;
-       struct smu_15_0_dpm_table *dclk_table =
-               &dpm_context->dpm_tables.dclk_table;
-       struct smu_15_0_dpm_table *fclk_table =
-               &dpm_context->dpm_tables.fclk_table;
+       struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
+       struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;
+       struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;
+       struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table;
+       struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table;
+       struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table;
        struct smu_umd_pstate_table *pstate_table =
                &smu->pstate_table;
        struct amdgpu_device *adev = smu->adev;
@@ -1084,34 +1078,34 @@ int smu_v15_0_set_performance_level(struct smu_context *smu,
 
        switch (level) {
        case AMD_DPM_FORCED_LEVEL_HIGH:
-               sclk_min = sclk_max = gfx_table->max;
-               mclk_min = mclk_max = mem_table->max;
-               socclk_min = socclk_max = soc_table->max;
-               vclk_min = vclk_max = vclk_table->max;
-               dclk_min = dclk_max = dclk_table->max;
-               fclk_min = fclk_max = fclk_table->max;
+               sclk_min = sclk_max = SMU_DPM_TABLE_MAX(gfx_table);
+               mclk_min = mclk_max = SMU_DPM_TABLE_MAX(mem_table);
+               socclk_min = socclk_max = SMU_DPM_TABLE_MAX(soc_table);
+               vclk_min = vclk_max = SMU_DPM_TABLE_MAX(vclk_table);
+               dclk_min = dclk_max = SMU_DPM_TABLE_MAX(dclk_table);
+               fclk_min = fclk_max = SMU_DPM_TABLE_MAX(fclk_table);
                break;
        case AMD_DPM_FORCED_LEVEL_LOW:
-               sclk_min = sclk_max = gfx_table->min;
-               mclk_min = mclk_max = mem_table->min;
-               socclk_min = socclk_max = soc_table->min;
-               vclk_min = vclk_max = vclk_table->min;
-               dclk_min = dclk_max = dclk_table->min;
-               fclk_min = fclk_max = fclk_table->min;
+               sclk_min = sclk_max = SMU_DPM_TABLE_MIN(gfx_table);
+               mclk_min = mclk_max = SMU_DPM_TABLE_MIN(mem_table);
+               socclk_min = socclk_max = SMU_DPM_TABLE_MIN(soc_table);
+               vclk_min = vclk_max = SMU_DPM_TABLE_MIN(vclk_table);
+               dclk_min = dclk_max = SMU_DPM_TABLE_MIN(dclk_table);
+               fclk_min = fclk_max = SMU_DPM_TABLE_MIN(fclk_table);
                break;
        case AMD_DPM_FORCED_LEVEL_AUTO:
-               sclk_min = gfx_table->min;
-               sclk_max = gfx_table->max;
-               mclk_min = mem_table->min;
-               mclk_max = mem_table->max;
-               socclk_min = soc_table->min;
-               socclk_max = soc_table->max;
-               vclk_min = vclk_table->min;
-               vclk_max = vclk_table->max;
-               dclk_min = dclk_table->min;
-               dclk_max = dclk_table->max;
-               fclk_min = fclk_table->min;
-               fclk_max = fclk_table->max;
+               sclk_min = SMU_DPM_TABLE_MIN(gfx_table);
+               sclk_max = SMU_DPM_TABLE_MAX(gfx_table);
+               mclk_min = SMU_DPM_TABLE_MIN(mem_table);
+               mclk_max = SMU_DPM_TABLE_MAX(mem_table);
+               socclk_min = SMU_DPM_TABLE_MIN(soc_table);
+               socclk_max = SMU_DPM_TABLE_MAX(soc_table);
+               vclk_min = SMU_DPM_TABLE_MIN(vclk_table);
+               vclk_max = SMU_DPM_TABLE_MAX(vclk_table);
+               dclk_min = SMU_DPM_TABLE_MIN(dclk_table);
+               dclk_max = SMU_DPM_TABLE_MAX(dclk_table);
+               fclk_min = SMU_DPM_TABLE_MIN(fclk_table);
+               fclk_max = SMU_DPM_TABLE_MAX(fclk_table);
                auto_level = true;
                break;
        case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
@@ -1333,10 +1327,11 @@ static int smu_v15_0_get_fine_grained_status(struct smu_context *smu,
 
 int smu_v15_0_set_single_dpm_table(struct smu_context *smu,
                                   enum smu_clk_type clk_type,
-                                  struct smu_15_0_dpm_table *single_dpm_table)
+                                  struct smu_dpm_table *single_dpm_table)
 {
        int ret = 0;
        uint32_t clk;
+       bool is_fine_grained;
        int i;
 
        ret = smu_v15_0_get_dpm_level_count(smu,
@@ -1349,12 +1344,15 @@ int smu_v15_0_set_single_dpm_table(struct smu_context *smu,
 
        ret = smu_v15_0_get_fine_grained_status(smu,
                                                clk_type,
-                                               &single_dpm_table->is_fine_grained);
+                                               &is_fine_grained);
        if (ret) {
                dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
                return ret;
        }
 
+       if (is_fine_grained)
+               single_dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;
+
        for (i = 0; i < single_dpm_table->count; i++) {
                ret = smu_v15_0_get_dpm_freq_by_index(smu,
                                                      clk_type,
@@ -1367,11 +1365,6 @@ int smu_v15_0_set_single_dpm_table(struct smu_context *smu,
 
                single_dpm_table->dpm_levels[i].value = clk;
                single_dpm_table->dpm_levels[i].enabled = true;
-
-               if (i == 0)
-                       single_dpm_table->min = clk;
-               else if (i == single_dpm_table->count - 1)
-                       single_dpm_table->max = clk;
        }
 
        return 0;