arm64: dts: qcom: sc7280: Describe the first PCIe controller and PHY

Only one PCIe controller has been described so far, but the SC7280 has
two controllers/phys. Describe the second one as well.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250811-sc7280-pcie0-v1-1-6093e5b208f9@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 97bb8a42a7b66a5a51428ab526fbe12a4b35e7ea..e38c2fbbecd5e59688f990759f47e2aa68c2e871 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2200,6 +2200,135 @@
                        qcom,smem-state-names = "wlan-smp2p-out";
                };
 
+               pcie0: pcie@1c00000 {
+                       compatible = "qcom,pcie-sc7280";
+                       reg = <0 0x01c00000 0 0x3000>,
+                             <0 0x60000000 0 0xf1d>,
+                             <0 0x60000f20 0 0xa8>,
+                             <0 0x60001000 0 0x1000>,
+                             <0 0x60100000 0 0x100000>,
+                             <0 0x01c03000 0 0x1000>;
+                       reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+                       device_type = "pci";
+                       linux,pci-domain = <0>;
+                       bus-range = <0x00 0xff>;
+                       num-lanes = <1>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+                                <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+
+                       interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi0",
+                                         "msi1",
+                                         "msi2",
+                                         "msi3",
+                                         "msi4",
+                                         "msi5",
+                                         "msi6",
+                                         "msi7",
+                                         "global";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
+
+                       clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+                                <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
+                                <&pcie0_phy>,
+                                <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GCC_PCIE_0_AUX_CLK>,
+                                <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                                <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+                                <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+                                <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+                                <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+                                <&gcc GCC_DDRSS_PCIE_SF_CLK>,
+                                <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
+                                <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
+                       clock-names = "pipe",
+                                     "pipe_mux",
+                                     "phy_pipe",
+                                     "ref",
+                                     "aux",
+                                     "cfg",
+                                     "bus_master",
+                                     "bus_slave",
+                                     "slave_q2a",
+                                     "tbu",
+                                     "ddrss_sf_tbu",
+                                     "aggre0",
+                                     "aggre1";
+
+                       iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
+                                   <0x100 &apps_smmu 0x1c01 0x1>;
+
+                       resets = <&gcc GCC_PCIE_0_BCR>;
+                       reset-names = "pci";
+
+                       power-domains = <&gcc GCC_PCIE_0_GDSC>;
+
+                       phys = <&pcie0_phy>;
+                       phy-names = "pciephy";
+
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pcie0_clkreq_n>;
+                       dma-coherent;
+
+                       status = "disabled";
+
+                       pcie0_port: pcie@0 {
+                               device_type = "pci";
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               bus-range = <0x01 0xff>;
+
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges;
+                       };
+               };
+
+               pcie0_phy: phy@1c06000 {
+                       compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
+                       reg = <0 0x01c06000 0 0x1000>;
+
+                       clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+                                <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                                <&gcc GCC_PCIE_CLKREF_EN>,
+                                <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
+                                <&gcc GCC_PCIE_0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "cfg_ahb",
+                                     "ref",
+                                     "refgen",
+                                     "pipe";
+
+                       clock-output-names = "pcie_0_pipe_clk";
+                       #clock-cells = <0>;
+
+                       #phy-cells = <0>;
+
+                       resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+                       reset-names = "phy";
+
+                       assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
+                       assigned-clock-rates = <100000000>;
+
+                       status = "disabled";
+               };
+
                pcie1: pcie@1c08000 {
                        compatible = "qcom,pcie-sc7280";
                        reg = <0 0x01c08000 0 0x3000>,
@@ -5279,6 +5408,11 @@
                                function = "mi2s1_ws";
                        };
 
+                       pcie0_clkreq_n: pcie0-clkreq-n-state {
+                               pins = "gpio88";
+                               function = "pcie0_clkreqn";
+                       };
+
                        pcie1_clkreq_n: pcie1-clkreq-n-state {
                                pins = "gpio79";
                                function = "pcie1_clkreqn";