clk: mediatek: rename HAVE_RST_BAR

Rename HAVE_RST_BAR to CLK_PLL_HAVE_RST_BAR. This makes it more clear
that this flag only applies to PLL clocks. Also add a blank line between
CLK_PLL_HAVE_RST_BAR and the CLK_MUX_ macros to keep the grouping of the
flags consistent.

Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-1-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>

diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 782eb14e9c507df2e94ba910e69f9c4c10573351..108c0dcd14ecff48b652547c345e85cffd931d85 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -48,9 +48,9 @@
 static const struct mtk_pll_data apmixed_plls[] = {
        PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
            21, 0x204, 24, 0x204, 0),
-       PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
+       PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, CLK_PLL_HAVE_RST_BAR,
            21, 0x214, 24, 0x214, 0),
-       PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
+       PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, CLK_PLL_HAVE_RST_BAR,
            7, 0x224, 24, 0x224, 14),
        PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
            21, 0x300, 1, 0x304, 0),

diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 071c4cf8a843d50f4d7b040a63d3e37c01c16878..70570644ca44b09f3616e39f5d6b51ac025232e0 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -61,9 +61,9 @@ static const int pll_id_offs_map[] = {
 static const struct mtk_pll_data apmixed_plls[] = {
        PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0,
            21, 0x204, 24, 0x204, 0),
-       PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR,
+       PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, CLK_PLL_HAVE_RST_BAR,
            21, 0x210, 4, 0x214, 0),
-       PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR,
+       PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, CLK_PLL_HAVE_RST_BAR,
            7, 0x220, 4, 0x224, 14),
        PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0,
            21, 0x230, 4, 0x234, 0),

diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index 582394f594bc01a5d6e6c3e93646a060f6bcea82..7fe62bdcea587e238eff4ace3b85eaaa3856f4f0 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -48,9 +48,9 @@
 static const struct mtk_pll_data apmixed_plls[] = {
        PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
            21, 0x204, 24, 0x204, 0),
-       PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
+       PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, CLK_PLL_HAVE_RST_BAR,
            21, 0x214, 24, 0x214, 0),
-       PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
+       PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, CLK_PLL_HAVE_RST_BAR,
            7, 0x224, 24, 0x224, 14),
        PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
            21, 0x300, 1, 0x304, 0),

diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 9d9d00622dbdc565b6af5056470c8cd5617016df..752cb1c61ab95a57e58fe3ddab3563a79d24006e 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -38,24 +38,24 @@
 
 static const struct mtk_pll_data apmixed_plls[] = {
        PLL(CLK_APMIXED_ARMPLL_LL, 0x0200, 0x020C, 0x00000001,
-           HAVE_RST_BAR, BIT(24), 22, 8, 0x0204, 24,
+           CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0204, 24,
            0x0204, 0),
        PLL(CLK_APMIXED_ARMPLL_L, 0x0210, 0x021C, 0x00000001,
-           HAVE_RST_BAR, BIT(24), 22, 8, 0x0214, 24,
+           CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0214, 24,
            0x0214, 0),
        PLL(CLK_APMIXED_CCIPLL, 0x0290, 0x029C, 0x00000001,
-           HAVE_RST_BAR, BIT(24), 22, 8, 0x0294, 24,
+           CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0294, 24,
            0x0294, 0),
        PLL(CLK_APMIXED_MAINPLL, 0x0220, 0x022C, 0x00000001,
-           HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24,
+           CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24,
            0x0224, 0),
        PLL(CLK_APMIXED_UNIV2PLL, 0x0230, 0x023C, 0x00000001,
-           HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24,
+           CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24,
            0x0234, 0),
        PLL(CLK_APMIXED_MSDCPLL, 0x0250, 0x025C, 0x00000001,
            0, 0, 22, 8, 0x0254, 24, 0x0254, 0),
        PLL(CLK_APMIXED_MMPLL, 0x0270, 0x027C, 0x00000001,
-           HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24,
+           CLK_PLL_HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24,
            0x0274, 0),
        PLL(CLK_APMIXED_MFGPLL, 0x0240, 0x024C, 0x00000001,
            0, 0, 22, 8, 0x0244, 24, 0x0244, 0),

diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c
index 803330717c6b266ba28d70f9872a33d053f1d739..3d20d2d93fc58e71c791aa03362951b54c022723 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -56,13 +56,13 @@ static const struct mtk_pll_data apmixed_plls[] = {
            0x0528, 0),
        PLL(CLK_APMIXED_TVDPLL2, 0x0534, 0x0540, 0, 0, 22, 0x0538, 24,
            0x0538, 0),
-       PLL(CLK_APMIXED_MMPLL, 0x0544, 0x0550, 0xff000000, HAVE_RST_BAR,
+       PLL(CLK_APMIXED_MMPLL, 0x0544, 0x0550, 0xff000000, CLK_PLL_HAVE_RST_BAR,
            22, 0x0548, 24, 0x0548, 0),
-       PLL(CLK_APMIXED_MAINPLL, 0x045C, 0x0468, 0xff000000, HAVE_RST_BAR,
+       PLL(CLK_APMIXED_MAINPLL, 0x045C, 0x0468, 0xff000000, CLK_PLL_HAVE_RST_BAR,
            22, 0x0460, 24, 0x0460, 0),
        PLL(CLK_APMIXED_IMGPLL, 0x0554, 0x0560, 0, 0, 22, 0x0558, 24,
            0x0558, 0),
-       PLL(CLK_APMIXED_UNIVPLL, 0x0504, 0x0510, 0xff000000, HAVE_RST_BAR,
+       PLL(CLK_APMIXED_UNIVPLL, 0x0504, 0x0510, 0xff000000, CLK_PLL_HAVE_RST_BAR,
            22, 0x0508, 24, 0x0508, 0),
        PLL(CLK_APMIXED_ADSPPLL, 0x042C, 0x0438, 0, 0, 22, 0x0430, 24,
            0x0430, 0),

diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c
index d05d56c9bf6c7dbc4e60784fb86030be9381bf90..d9d63601cc4cddfebb367b7ca185411e5ea11213 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8195.c
+++ b/drivers/clk/mediatek/clk-mt8195.c
@@ -62,15 +62,15 @@ static const struct mtk_pll_data apmixed_plls[] = {
            0x00a8, 0, 0x00a8),
        PLL(CLK_APMIXED_TVDPLL2, 0x00c0, 0x00d0, 0, 0, 0, 22, 0x00c8, 24,
            0x00c8, 0, 0x00c8),
-       PLL(CLK_APMIXED_MMPLL, 0x00e0, 0x00f0, 0xff000000, HAVE_RST_BAR,
+       PLL(CLK_APMIXED_MMPLL, 0x00e0, 0x00f0, 0xff000000, CLK_PLL_HAVE_RST_BAR,
            BIT(23), 22, 0x00e8, 24, 0x00e8, 0, 0x00e8),
-       PLL(CLK_APMIXED_MAINPLL, 0x01d0, 0x01e0, 0xff000000, HAVE_RST_BAR,
+       PLL(CLK_APMIXED_MAINPLL, 0x01d0, 0x01e0, 0xff000000, CLK_PLL_HAVE_RST_BAR,
            BIT(23), 22, 0x01d8, 24, 0x01d8, 0, 0x01d8),
        PLL(CLK_APMIXED_VDECPLL, 0x0890, 0x08a0, 0, 0, 0, 22, 0x0898, 24,
            0x0898, 0, 0x0898),
        PLL(CLK_APMIXED_IMGPLL, 0x0100, 0x0110, 0, 0, 0, 22, 0x0108, 24,
            0x0108, 0, 0x0108),
-       PLL(CLK_APMIXED_UNIVPLL, 0x01f0, 0x0700, 0xff000000, HAVE_RST_BAR,
+       PLL(CLK_APMIXED_UNIVPLL, 0x01f0, 0x0700, 0xff000000, CLK_PLL_HAVE_RST_BAR,
            BIT(23), 22, 0x01f8, 24, 0x01f8, 0, 0x01f8),
        PLL(CLK_APMIXED_HDMIPLL1, 0x08c0, 0x08d0, 0, 0, 0, 22, 0x08c8, 24,
            0x08c8, 0, 0x08c8),

diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c
index 6ba464097ae87f7c1bcfb5ee11865849e02e9456..2b1703e7203cf5665a54b8f8c4833f99270232bf 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8365.c
+++ b/drivers/clk/mediatek/clk-mt8365.c
@@ -45,9 +45,9 @@
 static const struct mtk_pll_data apmixed_plls[] = {
        PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, PLL_AO, 22, 0x0310,
            24, 0x0310, 0, 0, 0),
-       PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, HAVE_RST_BAR, 22,
+       PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, CLK_PLL_HAVE_RST_BAR, 22,
            0x022C, 24, 0x022C, 0, CON0_MT8365_RST_BAR, 0),
-       PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, HAVE_RST_BAR, 22,
+       PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, CLK_PLL_HAVE_RST_BAR, 22,
            0x020C, 24, 0x020C, 0, CON0_MT8365_RST_BAR, 0),
        PLL(CLK_APMIXED_MFGPLL, 0x0218, 0x0224, 0x00000001, 0, 22, 0x021C, 24,
            0x021C, 0, 0, 0),

diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c
index e6ced91fd06f76235f4bc52500ba4a0cfdf4c086..69576304f2f966f2de2410bb11def7d50676994c 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8512.c
+++ b/drivers/clk/mediatek/clk-mt8512.c
@@ -41,9 +41,9 @@ static const struct mtk_pll_data apmixed_plls[] = {
        PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001,
            0, 22, 0x0310, 24, 0x0310, 0, 0),
        PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x00000001,
-           HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0),
+           CLK_PLL_HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0),
        PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x00000001,
-           HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0),
+           CLK_PLL_HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0),
        PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001,
            0, 22, 0x0354, 24, 0x0354, 0, 0),
        PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001,

diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
index 4985ba3e5ce3e3e8c64b20b8890d8ae4363103b4..dac4aad61ef84cf220df0a837b1960885edb07f5 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8516.c
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -37,9 +37,9 @@ static const struct mtk_pll_data apmixed_plls[] = {
        PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0,
                21, 0x0104, 24, 0x0104, 0),
        PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
-               HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+               CLK_PLL_HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
        PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
-               HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+               CLK_PLL_HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
        PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0,
                21, 0x0164, 24, 0x0164, 0),
        PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0,

diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c
index 2fc492e717004ed5524b1725029169ae6fa2d9ee..c19828def064dff593e08f834678853df9bfd9aa 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8518.c
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -37,9 +37,9 @@ static const struct mtk_pll_data apmixed_plls[] = {
        PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001,
            0, 21, 0x0104, 24, 0x0104, 0),
        PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
-           HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+           CLK_PLL_HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
        PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
-           HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+           CLK_PLL_HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
        PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001,
            0, 21, 0x0164, 24, 0x0164, 0),
        PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001,

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 40eae634e02325c73f73b7e43e4ffcf7523ee9fe..cbe03f23388ecb9365c79e1518b587d5999c641f 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -598,7 +598,7 @@ static int mtk_apmixedsys_enable(struct clk *clk)
 
        udelay(20);
 
-       if (pll->flags & HAVE_RST_BAR) {
+       if (pll->flags & CLK_PLL_HAVE_RST_BAR) {
                r = readl(priv->base + pll->reg + REG_CON0);
                r |= pll->rst_bar_mask;
                writel(r, priv->base + pll->reg + REG_CON0);
@@ -622,7 +622,7 @@ static int mtk_apmixedsys_disable(struct clk *clk)
 
        pll = &priv->tree->plls[clk->id];
 
-       if (pll->flags & HAVE_RST_BAR) {
+       if (pll->flags & CLK_PLL_HAVE_RST_BAR) {
                r = readl(priv->base + pll->reg + REG_CON0);
                r &= ~pll->rst_bar_mask;
                writel(r, priv->base + pll->reg + REG_CON0);

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index c4aeee49abd7d09c74725f9dbdd7fdf4e28b46e7..806ec2ec20aa0ef583382b96c826a79834e1193c 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -20,7 +20,8 @@
  */
 #define CLK_BYPASS_XTAL                        BIT(0)
 
-#define HAVE_RST_BAR                   BIT(0)
+#define CLK_PLL_HAVE_RST_BAR           BIT(0)
+
 #define CLK_DOMAIN_SCPSYS              BIT(0)
 #define CLK_MUX_SETCLR_UPD             BIT(1)