clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks

[ Upstream commit 0d67c0340a60829c5c1b7d09629d23bbd67696f3 ]

I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
clk_register_composite() when registering the RPC[D2] clocks...

Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Link: https://lore.kernel.org/r/be27a344-d8bf-9e0c-8950-2d1b48498496@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index d25c8ba00a65684185a6a6b0f44de1f425709b58..532626946b8d274d986eeb0d38fedf67d05045d0 100644 (file)
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -464,7 +464,8 @@ static struct clk * __init cpg_rpc_clk_register(const char *name,
 
        clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
                                     &rpc->div.hw,  &clk_divider_ops,
-                                    &rpc->gate.hw, &clk_gate_ops, 0);
+                                    &rpc->gate.hw, &clk_gate_ops,
+                                    CLK_SET_RATE_PARENT);
        if (IS_ERR(clk)) {
                kfree(rpc);
                return clk;
@@ -500,7 +501,8 @@ static struct clk * __init cpg_rpcd2_clk_register(const char *name,
 
        clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
                                     &rpcd2->fixed.hw, &clk_fixed_factor_ops,
-                                    &rpcd2->gate.hw, &clk_gate_ops, 0);
+                                    &rpcd2->gate.hw, &clk_gate_ops,
+                                    CLK_SET_RATE_PARENT);
        if (IS_ERR(clk))
                kfree(rpcd2);