arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock

Add support for video, camera, display and gpu clock controller nodes
for QCS615 platform.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250814-qcs615-mm-cpu-dt-v6-v6-1-a06f69928ab5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi
index 69e013a17c9f9556f2cc504afefeb6b5f62e3325..d72647f0045b85b6960b814d3ce74869f681a320 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi
@@ -3,7 +3,11 @@
  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,qcs615-camcc.h>
+#include <dt-bindings/clock/qcom,qcs615-dispcc.h>
 #include <dt-bindings/clock/qcom,qcs615-gcc.h>
+#include <dt-bindings/clock/qcom,qcs615-gpucc.h>
+#include <dt-bindings/clock/qcom,qcs615-videocc.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
@@ -1662,6 +1666,19 @@
                        };
                };
 
+               gpucc: clock-controller@5090000 {
+                       compatible = "qcom,qcs615-gpucc";
+                       reg = <0 0x05090000 0 0x9000>;
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GPLL0>,
+                                <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                stm@6002000 {
                        compatible = "arm,coresight-stm", "arm,primecell";
                        reg = <0x0 0x06002000 0x0 0x1000>,
@@ -3523,6 +3540,46 @@
                        qcom,bcm-voters = <&apps_bcm_voter>;
                };
 
+               videocc: clock-controller@ab00000 {
+                       compatible = "qcom,qcs615-videocc";
+                       reg = <0 0x0ab00000 0 0x10000>;
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <&sleep_clk>;
+
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
+               camcc: clock-controller@ad00000 {
+                       compatible = "qcom,qcs615-camcc";
+                       reg = <0 0x0ad00000 0 0x10000>;
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>;
+
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
+               dispcc: clock-controller@af00000 {
+                       compatible = "qcom,qcs615-dispcc";
+                       reg = <0 0x0af00000 0 0x20000>;
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+                                <0>,
+                                <0>,
+                                <0>,
+                                <0>,
+                                <0>;
+
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                pdc: interrupt-controller@b220000 {
                        compatible = "qcom,qcs615-pdc", "qcom,pdc";
                        reg = <0x0 0x0b220000 0x0 0x30000>,