--- /dev/null
+From c646d10dda2dcde82c6ce5a474522621ab2b8b19 Mon Sep 17 00:00:00 2001
+From: Vladimir Oltean <vladimir.oltean@nxp.com>
+Date: Mon, 1 Mar 2021 13:18:11 +0200
+Subject: net: enetc: don't overwrite the RSS indirection table when initializing
+
+From: Vladimir Oltean <vladimir.oltean@nxp.com>
+
+commit c646d10dda2dcde82c6ce5a474522621ab2b8b19 upstream.
+
+After the blamed patch, all RX traffic gets hashed to CPU 0 because the
+hashing indirection table set up in:
+
+enetc_pf_probe
+-> enetc_alloc_si_resources
+ -> enetc_configure_si
+ -> enetc_setup_default_rss_table
+
+is overwritten later in:
+
+enetc_pf_probe
+-> enetc_init_port_rss_memory
+
+which zero-initializes the entire port RSS table in order to avoid ECC errors.
+
+The trouble really is that enetc_init_port_rss_memory really neads
+enetc_alloc_si_resources to be called, because it depends upon
+enetc_alloc_cbdr and enetc_setup_cbdr. But that whole enetc_configure_si
+thing could have been better thought out, it has nothing to do in a
+function called "alloc_si_resources", especially since its counterpart,
+"free_si_resources", does nothing to unwind the configuration of the SI.
+
+The point is, we need to pull out enetc_configure_si out of
+enetc_alloc_resources, and move it after enetc_init_port_rss_memory.
+This allows us to set up the default RSS indirection table after
+initializing the memory.
+
+Fixes: 07bf34a50e32 ("net: enetc: initialize the RFS and RSS memories")
+Cc: Jesse Brandeburg <jesse.brandeburg@intel.com>
+Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/ethernet/freescale/enetc/enetc.c | 11 +++--------
+ drivers/net/ethernet/freescale/enetc/enetc.h | 1 +
+ drivers/net/ethernet/freescale/enetc/enetc_pf.c | 7 +++++++
+ drivers/net/ethernet/freescale/enetc/enetc_vf.c | 7 +++++++
+ 4 files changed, 18 insertions(+), 8 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/enetc/enetc.c
++++ b/drivers/net/ethernet/freescale/enetc/enetc.c
+@@ -1016,13 +1016,12 @@ static int enetc_setup_default_rss_table
+ return 0;
+ }
+
+-static int enetc_configure_si(struct enetc_ndev_priv *priv)
++int enetc_configure_si(struct enetc_ndev_priv *priv)
+ {
+ struct enetc_si *si = priv->si;
+ struct enetc_hw *hw = &si->hw;
+ int err;
+
+- enetc_setup_cbdr(hw, &si->cbd_ring);
+ /* set SI cache attributes */
+ enetc_wr(hw, ENETC_SICAR0,
+ ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);
+@@ -1068,6 +1067,8 @@ int enetc_alloc_si_resources(struct enet
+ if (err)
+ return err;
+
++ enetc_setup_cbdr(&si->hw, &si->cbd_ring);
++
+ priv->cls_rules = kcalloc(si->num_fs_entries, sizeof(*priv->cls_rules),
+ GFP_KERNEL);
+ if (!priv->cls_rules) {
+@@ -1075,14 +1076,8 @@ int enetc_alloc_si_resources(struct enet
+ goto err_alloc_cls;
+ }
+
+- err = enetc_configure_si(priv);
+- if (err)
+- goto err_config_si;
+-
+ return 0;
+
+-err_config_si:
+- kfree(priv->cls_rules);
+ err_alloc_cls:
+ enetc_clear_cbdr(&si->hw);
+ enetc_free_cbdr(priv->dev, &si->cbd_ring);
+--- a/drivers/net/ethernet/freescale/enetc/enetc.h
++++ b/drivers/net/ethernet/freescale/enetc/enetc.h
+@@ -221,6 +221,7 @@ void enetc_get_si_caps(struct enetc_si *
+ void enetc_init_si_rings_params(struct enetc_ndev_priv *priv);
+ int enetc_alloc_si_resources(struct enetc_ndev_priv *priv);
+ void enetc_free_si_resources(struct enetc_ndev_priv *priv);
++int enetc_configure_si(struct enetc_ndev_priv *priv);
+
+ int enetc_open(struct net_device *ndev);
+ int enetc_close(struct net_device *ndev);
+--- a/drivers/net/ethernet/freescale/enetc/enetc_pf.c
++++ b/drivers/net/ethernet/freescale/enetc/enetc_pf.c
+@@ -920,6 +920,12 @@ static int enetc_pf_probe(struct pci_dev
+ goto err_init_port_rss;
+ }
+
++ err = enetc_configure_si(priv);
++ if (err) {
++ dev_err(&pdev->dev, "Failed to configure SI\n");
++ goto err_config_si;
++ }
++
+ err = enetc_alloc_msix(priv);
+ if (err) {
+ dev_err(&pdev->dev, "MSIX alloc failed\n");
+@@ -945,6 +951,7 @@ err_reg_netdev:
+ enetc_mdio_remove(pf);
+ enetc_of_put_phy(priv);
+ enetc_free_msix(priv);
++err_config_si:
+ err_init_port_rss:
+ err_init_port_rfs:
+ err_alloc_msix:
+--- a/drivers/net/ethernet/freescale/enetc/enetc_vf.c
++++ b/drivers/net/ethernet/freescale/enetc/enetc_vf.c
+@@ -189,6 +189,12 @@ static int enetc_vf_probe(struct pci_dev
+ goto err_alloc_si_res;
+ }
+
++ err = enetc_configure_si(priv);
++ if (err) {
++ dev_err(&pdev->dev, "Failed to configure SI\n");
++ goto err_config_si;
++ }
++
+ err = enetc_alloc_msix(priv);
+ if (err) {
+ dev_err(&pdev->dev, "MSIX alloc failed\n");
+@@ -208,6 +214,7 @@ static int enetc_vf_probe(struct pci_dev
+
+ err_reg_netdev:
+ enetc_free_msix(priv);
++err_config_si:
+ err_alloc_msix:
+ enetc_free_si_resources(priv);
+ err_alloc_si_res:
--- /dev/null
+From 8c91bc3d44dfef8284af384877fbe61117e8b7d1 Mon Sep 17 00:00:00 2001
+From: Sergey Shtylyov <s.shtylyov@omprussia.ru>
+Date: Sun, 28 Feb 2021 23:25:43 +0300
+Subject: sh_eth: fix TRSCER mask for SH771x
+
+From: Sergey Shtylyov <s.shtylyov@omprussia.ru>
+
+commit 8c91bc3d44dfef8284af384877fbe61117e8b7d1 upstream.
+
+According to the SH7710, SH7712, SH7713 Group User's Manual: Hardware,
+Rev. 3.00, the TRSCER register actually has only bit 7 valid (and named
+differently), with all the other bits reserved. Apparently, this was not
+the case with some early revisions of the manual as we have the other
+bits declared (and set) in the original driver. Follow the suit and add
+the explicit sh_eth_cpu_data::trscer_err_mask initializer for SH771x...
+
+Fixes: 86a74ff21a7a ("net: sh_eth: add support for Renesas SuperH Ethernet")
+Signed-off-by: Sergey Shtylyov <s.shtylyov@omprussia.ru>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -1131,6 +1131,9 @@ static struct sh_eth_cpu_data sh771x_dat
+ EESIPR_CEEFIP | EESIPR_CELFIP |
+ EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
+ EESIPR_PREIP | EESIPR_CERFIP,
++
++ .trscer_err_mask = DESC_I_RINT8,
++
+ .tsu = 1,
+ .dual_port = 1,
+ };