]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
3.0 patches
authorGreg Kroah-Hartman <gregkh@suse.de>
Mon, 17 Oct 2011 18:56:20 +0000 (11:56 -0700)
committerGreg Kroah-Hartman <gregkh@suse.de>
Mon, 17 Oct 2011 18:56:20 +0000 (11:56 -0700)
queue-3.0/arm-7113-1-mm-align-bank-start-to-max_order_nr_pages.patch [new file with mode: 0644]
queue-3.0/arm-7117-1-perf-fix-hw_cache_-events-on-cortex-a9.patch [new file with mode: 0644]
queue-3.0/hwmon-w83627ehf-properly-report-thermal-diode-sensors.patch [new file with mode: 0644]
queue-3.0/series

diff --git a/queue-3.0/arm-7113-1-mm-align-bank-start-to-max_order_nr_pages.patch b/queue-3.0/arm-7113-1-mm-align-bank-start-to-max_order_nr_pages.patch
new file mode 100644 (file)
index 0000000..988be37
--- /dev/null
@@ -0,0 +1,44 @@
+From 002ea9eefec98dada56fd5f8e432a4e8570c2a26 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 29 Sep 2011 09:37:23 +0100
+Subject: ARM: 7113/1: mm: Align bank start to MAX_ORDER_NR_PAGES
+
+From: Linus Walleij <linus.walleij@linaro.org>
+
+commit 002ea9eefec98dada56fd5f8e432a4e8570c2a26 upstream.
+
+The VM subsystem assumes that there are valid memmap entries from
+the bank start aligned to MAX_ORDER_NR_PAGES.
+
+On the Ux500 we have a lot of mem=N arguments on the commandline
+triggering this bug several times over and causing kernel
+oops messages.
+
+Cc: Michael Bohan <mbohan@codeaurora.org>
+Cc: Nicolas Pitre <nico@fluxnic.net>
+Signed-off-by: Johan Palsson <johan.palsson@stericsson.com>
+Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ arch/arm/mm/init.c |    7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/arm/mm/init.c
++++ b/arch/arm/mm/init.c
+@@ -473,6 +473,13 @@ static void __init free_unused_memmap(st
+                */
+               bank_start = min(bank_start,
+                                ALIGN(prev_bank_end, PAGES_PER_SECTION));
++#else
++              /*
++               * Align down here since the VM subsystem insists that the
++               * memmap entries are valid from the bank start aligned to
++               * MAX_ORDER_NR_PAGES.
++               */
++              bank_start = round_down(bank_start, MAX_ORDER_NR_PAGES);
+ #endif
+               /*
+                * If we had a previous bank, and there is a space
diff --git a/queue-3.0/arm-7117-1-perf-fix-hw_cache_-events-on-cortex-a9.patch b/queue-3.0/arm-7117-1-perf-fix-hw_cache_-events-on-cortex-a9.patch
new file mode 100644 (file)
index 0000000..62f00c9
--- /dev/null
@@ -0,0 +1,39 @@
+From 29a541f6c1f6e4a85628bb86071b9e72c9f8be2c Mon Sep 17 00:00:00 2001
+From: Will Deacon <will.deacon@arm.com>
+Date: Mon, 3 Oct 2011 18:30:53 +0100
+Subject: ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9
+
+From: Will Deacon <will.deacon@arm.com>
+
+commit 29a541f6c1f6e4a85628bb86071b9e72c9f8be2c upstream.
+
+Using COHERENT_LINE_{MISS,HIT} for cache misses and references
+respectively is completely wrong. Instead, use the L1D events which
+are a better and more useful approximation despite ignoring instruction
+traffic.
+
+Reported-by: Alasdair Grant <alasdair.grant@arm.com>
+Reported-by: Matt Horsnell <matt.horsnell@arm.com>
+Reported-by: Michael Williams <michael.williams@arm.com>
+Cc: Jean Pihet <j-pihet@ti.com>
+Signed-off-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ arch/arm/kernel/perf_event_v7.c |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/kernel/perf_event_v7.c
++++ b/arch/arm/kernel/perf_event_v7.c
+@@ -264,8 +264,8 @@ static const unsigned armv7_a9_perf_map[
+       [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+       [PERF_COUNT_HW_INSTRUCTIONS]        =
+                                       ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
+-      [PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_COHERENT_LINE_HIT,
+-      [PERF_COUNT_HW_CACHE_MISSES]        = ARMV7_PERFCTR_COHERENT_LINE_MISS,
++      [PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_DCACHE_ACCESS,
++      [PERF_COUNT_HW_CACHE_MISSES]        = ARMV7_PERFCTR_DCACHE_REFILL,
+       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+       [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+       [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
diff --git a/queue-3.0/hwmon-w83627ehf-properly-report-thermal-diode-sensors.patch b/queue-3.0/hwmon-w83627ehf-properly-report-thermal-diode-sensors.patch
new file mode 100644 (file)
index 0000000..83bbc56
--- /dev/null
@@ -0,0 +1,67 @@
+From bf164c58e58328c40ebc597a8ac00cc6840f9703 Mon Sep 17 00:00:00 2001
+From: Jean Delvare <khali@linux-fr.org>
+Date: Thu, 13 Oct 2011 15:49:08 -0400
+Subject: hwmon: (w83627ehf) Properly report thermal diode sensors
+
+From: Jean Delvare <khali@linux-fr.org>
+
+commit bf164c58e58328c40ebc597a8ac00cc6840f9703 upstream.
+
+The w83627ehf driver is improperly reporting thermal diode sensors as
+type 2, instead of 3. This caused "sensors" and possibly other
+monitoring tools to report these sensors as "transistor" instead of
+"thermal diode".
+
+Furthermore, diode subtype selection (CPU vs. external) is only
+supported by the original W83627EHF/EHG. All later models only support
+CPU diode type, and some (NCT6776F) don't even have the register in
+question so we should avoid reading from it.
+
+Signed-off-by: Jean Delvare <khali@linux-fr.org>
+Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/hwmon/w83627ehf.c |   15 +++++++++++----
+ 1 file changed, 11 insertions(+), 4 deletions(-)
+
+--- a/drivers/hwmon/w83627ehf.c
++++ b/drivers/hwmon/w83627ehf.c
+@@ -1715,7 +1715,8 @@ static void w83627ehf_device_remove_file
+ }
+ /* Get the monitoring functions started */
+-static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data)
++static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data,
++                                                 enum kinds kind)
+ {
+       int i;
+       u8 tmp, diode;
+@@ -1746,10 +1747,16 @@ static inline void __devinit w83627ehf_i
+               w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
+       /* Get thermal sensor types */
+-      diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
++      switch (kind) {
++      case w83627ehf:
++              diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
++              break;
++      default:
++              diode = 0x70;
++      }
+       for (i = 0; i < 3; i++) {
+               if ((tmp & (0x02 << i)))
+-                      data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 2;
++                      data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
+               else
+                       data->temp_type[i] = 4; /* thermistor */
+       }
+@@ -2016,7 +2023,7 @@ static int __devinit w83627ehf_probe(str
+       }
+       /* Initialize the chip */
+-      w83627ehf_init_device(data);
++      w83627ehf_init_device(data, sio_data->kind);
+       data->vrm = vid_which_vrm();
+       superio_enter(sio_data->sioreg);
index 450c5faf3421ee3895a07a6a16f05854c154b78a..e0a9ae20085fba05b54c6daf56794c89424cd2dc 100644 (file)
@@ -1 +1,4 @@
+arm-7113-1-mm-align-bank-start-to-max_order_nr_pages.patch
+arm-7117-1-perf-fix-hw_cache_-events-on-cortex-a9.patch
 hid-usbhid-add-support-for-sigma-micro-chip.patch
+hwmon-w83627ehf-properly-report-thermal-diode-sensors.patch