static void rteth_set_mac_hw(struct net_device *dev, u8 *mac)
{
- struct rteth_ctrl *ctrl = netdev_priv(dev);
+ u32 mac_lo = (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];
+ u32 mac_hi = (mac[0] << 8) | mac[1];
+ struct rteth_ctrl *ctrl;
unsigned long flags;
+ ctrl = netdev_priv(dev);
spin_lock_irqsave(&ctrl->lock, flags);
- pr_debug("In %s\n", __func__);
- sw_w32((mac[0] << 8) | mac[1], ctrl->r->mac);
- sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], ctrl->r->mac + 4);
- if (ctrl->r->family_id == RTL8380_FAMILY_ID) {
- /* 2 more registers, ALE/MAC block */
- sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE);
- sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
- (RTL838X_MAC_ALE + 4));
-
- sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2);
- sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
- RTL838X_MAC2 + 4);
- }
+ for (int i = 0; i < RTETH_MAX_MAC_REGS; i++)
+ if (ctrl->r->mac_reg[i]) {
+ sw_w32(mac_hi, ctrl->r->mac_reg[i]);
+ sw_w32(mac_lo, ctrl->r->mac_reg[i] + 4);
+ }
+
spin_unlock_irqrestore(&ctrl->lock, flags);
}
.get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,
.get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,
.get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,
- .mac = RTL838X_MAC,
+ .mac_reg = { RTETH_838X_MAC_ADDR_CTRL,
+ RTETH_838X_MAC_ADDR_CTRL_ALE,
+ RTETH_838X_MAC_ADDR_CTRL_MAC },
.l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
.update_counter = rteth_83xx_update_counter,
.create_tx_header = rteth_838x_create_tx_header,
.get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,
.get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,
.get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,
- .mac = RTL839X_MAC,
+ .mac_reg = { RTETH_839X_MAC_ADDR_CTRL },
.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
.update_counter = rteth_83xx_update_counter,
.create_tx_header = rteth_839x_create_tx_header,
.get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts,
.get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts,
.get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts,
- .mac = RTL930X_MAC_L2_ADDR_CTRL,
+ .mac_reg = { RTETH_930X_MAC_L2_ADDR_CTRL },
.l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
.update_counter = rteth_93xx_update_counter,
.create_tx_header = rteth_930x_create_tx_header,
.get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts,
.get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts,
.get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts,
- .mac = RTL931X_MAC_L2_ADDR_CTRL,
+ .mac_reg = { RTETH_930X_MAC_L2_ADDR_CTRL },
.l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
.update_counter = rteth_93xx_update_counter,
.create_tx_header = rteth_931x_create_tx_header,
if (is_valid_ether_addr(mac_addr)) {
rteth_set_mac_hw(dev, mac_addr);
} else {
- mac_addr[0] = (sw_r32(ctrl->r->mac) >> 8) & 0xff;
- mac_addr[1] = sw_r32(ctrl->r->mac) & 0xff;
- mac_addr[2] = (sw_r32(ctrl->r->mac + 4) >> 24) & 0xff;
- mac_addr[3] = (sw_r32(ctrl->r->mac + 4) >> 16) & 0xff;
- mac_addr[4] = (sw_r32(ctrl->r->mac + 4) >> 8) & 0xff;
- mac_addr[5] = sw_r32(ctrl->r->mac + 4) & 0xff;
+ mac_addr[0] = (sw_r32(ctrl->r->mac_reg[0]) >> 8) & 0xff;
+ mac_addr[1] = sw_r32(ctrl->r->mac_reg[0]) & 0xff;
+ mac_addr[2] = (sw_r32(ctrl->r->mac_reg[0] + 4) >> 24) & 0xff;
+ mac_addr[3] = (sw_r32(ctrl->r->mac_reg[0] + 4) >> 16) & 0xff;
+ mac_addr[4] = (sw_r32(ctrl->r->mac_reg[0] + 4) >> 8) & 0xff;
+ mac_addr[5] = sw_r32(ctrl->r->mac_reg[0] + 4) & 0xff;
}
dev_addr_set(dev, mac_addr);
/* if the address is invalid, use a random value */
#ifndef _RTL838X_ETH_H
#define _RTL838X_ETH_H
+#define RTETH_MAX_MAC_REGS 3
+
/* Register definition */
#define RTETH_838X_CPU_PORT 28
#define RTETH_838X_DMA_IF_INTR_MSK (0x9f50)
#define RTETH_838X_DMA_IF_INTR_STS (0x9f54)
+#define RTETH_838X_MAC_ADDR_CTRL (0xa9ec)
+#define RTETH_838X_MAC_ADDR_CTRL_ALE (0x6b04)
+#define RTETH_838X_MAC_ADDR_CTRL_MAC (0xa320)
#define RTETH_838X_MAC_FORCE_MODE_CTRL (0xa104 + RTETH_838X_CPU_PORT * 4)
#define RTETH_838X_MAC_L2_PORT_CTRL (0xd560 + RTETH_838X_CPU_PORT * 128)
#define RTETH_838X_QM_PKT2CPU_INTPRI_MAP (0x5f10)
#define RTETH_839X_CPU_PORT 52
#define RTETH_839X_DMA_IF_INTR_MSK (0x7864)
#define RTETH_839X_DMA_IF_INTR_STS (0x7868)
+#define RTETH_839X_MAC_ADDR_CTRL (0x02b4)
#define RTETH_839X_MAC_FORCE_MODE_CTRL (0x02bc + RTETH_839X_CPU_PORT * 4)
#define RTETH_839X_MAC_L2_PORT_CTRL (0x8004 + RTETH_839X_CPU_PORT * 128)
#define RTETH_839X_QM_PKT2CPU_INTPRI_MAP (0x1154)
#define RTETH_930X_DMA_IF_INTR_MSK (0xe010)
#define RTETH_930X_DMA_IF_INTR_STS (0xe01c)
#define RTETH_930X_MAC_FORCE_MODE_CTRL (0xca1c + RTETH_930X_CPU_PORT * 4)
+#define RTETH_930X_MAC_L2_ADDR_CTRL (0xc714)
#define RTETH_930X_MAC_L2_PORT_CTRL (0x3268 + RTETH_930X_CPU_PORT * 64)
#define RTETH_930X_QM_RSN2CPUQID_CTRL_0 (0xa344)
#define RTETH_930X_QM_RSN2CPUQID_CTRL_CNT 11
#define RTETH_931X_DMA_IF_INTR_MSK (0x0910)
#define RTETH_931X_DMA_IF_INTR_STS (0x091c)
#define RTETH_931X_MAC_FORCE_MODE_CTRL (0x0dcc + RTETH_931X_CPU_PORT * 4)
+#define RTETH_931X_MAC_L2_ADDR_CTRL (0x135c)
#define RTETH_931X_MAC_L2_PORT_CTRL (0x6000 + RTETH_931X_CPU_PORT * 128)
#define RTETH_931X_QM_RSN2CPUQID_CTRL_0 (0xa9f4)
#define RTETH_931X_QM_RSN2CPUQID_CTRL_CNT 14
#define RTL839X_DMA_IF_INTR_NOTIFY_MASK GENMASK(22, 20)
-/* MAC address settings */
-#define RTL838X_MAC (0xa9ec)
-#define RTL839X_MAC (0x02b4)
-#define RTL838X_MAC_ALE (0x6b04)
-#define RTL838X_MAC2 (0xa320)
-#define RTL930X_MAC_L2_ADDR_CTRL (0xC714)
-#define RTL931X_MAC_L2_ADDR_CTRL (0x135c)
-
/* Ringbuffer setup */
#define RTL838X_DMA_RX_BASE (0x9f00)
#define RTL839X_DMA_RX_BASE (0x780c)
u32 (*get_mac_link_spd_sts)(int port);
u32 (*get_mac_rx_pause_sts)(int port);
u32 (*get_mac_tx_pause_sts)(int port);
- int mac;
+ u32 mac_reg[RTETH_MAX_MAC_REGS];
int l2_tbl_flush_ctrl;
void (*create_tx_header)(struct rteth_packet *h, unsigned int dest_port, int prio);
bool (*decode_tag)(struct rteth_packet *h, struct dsa_tag *tag);