--- /dev/null
+From 064b43304ed8ede8e13ff7b4338d09fd37bcffb1 Mon Sep 17 00:00:00 2001
+From: Carolyn Wyborny <carolyn.wyborny@intel.com>
+Date: Sat, 25 Jun 2011 13:18:12 +0000
+Subject: igb: Fix lack of flush after register write and before delay
+
+From: Carolyn Wyborny <carolyn.wyborny@intel.com>
+
+commit 064b43304ed8ede8e13ff7b4338d09fd37bcffb1 upstream.
+
+Register writes followed by a delay are required to have a flush
+before the delay in order to commit the values to the register. Without
+the flush, the code following the delay may not function correctly.
+
+Reported-by: Tong Ho <tong.ho@ericsson.com>
+Reported-by: Guenter Roeck <guenter.roeck@ericsson.com>
+Signed-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com>
+Tested-by: Aaron Brown <aaron.f.brown@intel.com>
+Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/net/igb/e1000_82575.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/net/igb/e1000_82575.c
++++ b/drivers/net/igb/e1000_82575.c
+@@ -1735,6 +1735,7 @@ static s32 igb_reset_hw_82580(struct e10
+ ctrl |= E1000_CTRL_RST;
+
+ wr32(E1000_CTRL, ctrl);
++ wrfl();
+
+ /* Add delay to insure DEV_RST has time to complete */
+ if (global_device_reset)
fuse-check-size-of-fuse_notify_inval_entry-message.patch
rt2x00-fix-order-of-entry-flags-modification.patch
mmc-sdhci-fix-retuning-timer-wrongly-deleted-in.patch
+igb-fix-lack-of-flush-after-register-write-and-before-delay.patch