drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields

On Xe3p_LPD, the dbuf blocks fields of different registers are now
documented as 13-bit fields. The dbuf isn't really large enough to need
the 13th bit, but let's go ahead and update the definition now just in
case some new display IP in future ends up needing the larger size. The
extra bit is an unused bit in previous display versions, so we can
safely just extend the existing definition.

Bspec: 69847, 69880, 72053
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-5-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 7c944d3ca85550fcd53af1798607ac8b3e3c538b..6f815b2313404166349d4bcc61b776ab71c6756e 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -324,7 +324,7 @@
 #define   PLANE_WM_IGNORE_LINES                        REG_BIT(30)
 #define   PLANE_WM_AUTO_MIN_ALLOC_EN           REG_BIT(29)
 #define   PLANE_WM_LINES_MASK                  REG_GENMASK(26, 14)
-#define   PLANE_WM_BLOCKS_MASK                 REG_GENMASK(11, 0)
+#define   PLANE_WM_BLOCKS_MASK                 REG_GENMASK(12, 0)
 
 #define _PLANE_WM_SAGV_1_A                     0x70258
 #define _PLANE_WM_SAGV_1_B                     0x71258
@@ -375,10 +375,10 @@
                                                        _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B, \
                                                        _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
 
-/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
-#define   PLANE_BUF_END_MASK                   REG_GENMASK(27, 16)
+/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits, xe3p_lpd 13 bits */
+#define   PLANE_BUF_END_MASK                   REG_GENMASK(28, 16)
 #define   PLANE_BUF_END(end)                   REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
-#define   PLANE_BUF_START_MASK                 REG_GENMASK(11, 0)
+#define   PLANE_BUF_START_MASK                 REG_GENMASK(12, 0)
 #define   PLANE_BUF_START(start)               REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
 
 #define _PLANE_MIN_BUF_CFG_1_A                 0x70274
@@ -389,9 +389,9 @@
                                                        _PLANE_MIN_BUF_CFG_1_A, _PLANE_MIN_BUF_CFG_1_B, \
                                                        _PLANE_MIN_BUF_CFG_2_A, _PLANE_MIN_BUF_CFG_2_B)
 #define          PLANE_AUTO_MIN_DBUF_EN                REG_BIT(31)
-#define          PLANE_MIN_DBUF_BLOCKS_MASK            REG_GENMASK(27, 16)
+#define          PLANE_MIN_DBUF_BLOCKS_MASK            REG_GENMASK(28, 16)
 #define          PLANE_MIN_DBUF_BLOCKS(val)            REG_FIELD_PREP(PLANE_MIN_DBUF_BLOCKS_MASK, (val))
-#define          PLANE_INTERIM_DBUF_BLOCKS_MASK        REG_GENMASK(11, 0)
+#define          PLANE_INTERIM_DBUF_BLOCKS_MASK        REG_GENMASK(12, 0)
 #define          PLANE_INTERIM_DBUF_BLOCKS(val)        REG_FIELD_PREP(PLANE_INTERIM_DBUF_BLOCKS_MASK, (val))
 
 /* tgl+ */