EDAC/altera: Handle OCRAM ECC enable after warm reset

The OCRAM ECC is always enabled either by the BootROM or by the Secure Device
Manager (SDM) during a power-on reset on SoCFPGA.

However, during a warm reset, the OCRAM content is retained to preserve data,
while the control and status registers are reset to their default values. As
a result, ECC must be explicitly re-enabled after a warm reset.

Fixes: 17e47dc6db4f ("EDAC/altera: Add Stratix10 OCRAM ECC support")
Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20251111080801.1279401-1-niravkumarlaxmidas.rabara@altera.com

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 103b2c2eba2aba49ef9b1dc6752ba83ee8ea7230..a776d61027f29ea325026151fba699c93d9a2a17 100644 (file)
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1184,10 +1184,22 @@ altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
        if (ret)
                return ret;
 
-       /* Verify OCRAM has been initialized */
+       /*
+        * Verify that OCRAM has been initialized.
+        * During a warm reset, OCRAM contents are retained, but the control
+        * and status registers are reset to their default values. Therefore,
+        * ECC must be explicitly re-enabled in the control register.
+        * Error condition: if INITCOMPLETEA is clear and ECC_EN is already set.
+        */
        if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
-                          (base + ALTR_A10_ECC_INITSTAT_OFST)))
-               return -ENODEV;
+                          (base + ALTR_A10_ECC_INITSTAT_OFST))) {
+               if (!ecc_test_bits(ALTR_A10_ECC_EN,
+                                  (base + ALTR_A10_ECC_CTRL_OFST)))
+                       ecc_set_bits(ALTR_A10_ECC_EN,
+                                    (base + ALTR_A10_ECC_CTRL_OFST));
+               else
+                       return -ENODEV;
+       }
 
        /* Enable IRQ on Single Bit Error */
        writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));