drm/msm/dsi/phy: fix hardware revision

The hardware revision for TSMC 3nm-based Qualcomm SOCs should be 7.2,
this can be confirmed from REG_DSI_7nm_PHY_CMN_REVISION_ID0, the value
is 0x27, which means hardware revision is 7.2

No functional change.

Fixes: 1337d7ebfb6d ("drm/msm/dsi/phy: Add support for SM8750")
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/707414/
Link: https://lore.kernel.org/r/20260226122958.22555-2-mitltlatltl@gmail.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 8cb0db3a98808b5c817a3d296e19df86d9d73492..01182442dfd611f8db66c9774c71d3bbfc33db22 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -51,8 +51,8 @@
 #define DSI_PHY_7NM_QUIRK_V4_3         BIT(3)
 /* Hardware is V5.2 */
 #define DSI_PHY_7NM_QUIRK_V5_2         BIT(4)
-/* Hardware is V7.0 */
-#define DSI_PHY_7NM_QUIRK_V7_0         BIT(5)
+/* Hardware is V7.2 */
+#define DSI_PHY_7NM_QUIRK_V7_2         BIT(5)
 
 struct dsi_pll_config {
        bool enable_ssc;
@@ -143,7 +143,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
 
        if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) {
                config->pll_clock_inverters = 0x28;
-       } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
+       } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)) {
                if (pll_freq < 163000000ULL)
                        config->pll_clock_inverters = 0xa0;
                else if (pll_freq < 175000000ULL)
@@ -284,7 +284,7 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
        }
 
        if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
-           (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
+           (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)) {
                if (pll->vco_current_rate < 1557000000ULL)
                        vco_config_1 = 0x08;
                else
@@ -699,7 +699,7 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
        case MSM_DSI_PHY_MASTER:
                pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX];
                /* v7.0: Enable ATB_EN0 and alternate clock output to external phy */
-               if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)
+               if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)
                        writel(0x07, base + REG_DSI_7nm_PHY_CMN_CTRL_5);
                break;
        case MSM_DSI_PHY_SLAVE:
@@ -987,7 +987,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
        /* Request for REFGEN READY */
        if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
            (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
-           (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
+           (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)) {
                writel(0x1, phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10);
                udelay(500);
        }
@@ -1021,7 +1021,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
                lane_ctrl0 = 0x1f;
        }
 
-       if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
+       if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)) {
                if (phy->cphy_mode) {
                        /* TODO: different for second phy */
                        vreg_ctrl_0 = 0x57;
@@ -1097,7 +1097,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
 
        /* program CMN_CTRL_4 for minor_ver 2 chipsets*/
        if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
-           (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0) ||
+           (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2) ||
            (readl(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20)
                writel(0x04, base + REG_DSI_7nm_PHY_CMN_CTRL_4);
 
@@ -1213,7 +1213,7 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
        /* Turn off REFGEN Vote */
        if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
            (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
-           (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
+           (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)) {
                writel(0x0, base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10);
                wmb();
                /* Delay to ensure HW removes vote before PHY shut down */
@@ -1502,7 +1502,7 @@ const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs = {
 #endif
        .io_start = { 0xae95000, 0xae97000 },
        .num_dsi_phy = 2,
-       .quirks = DSI_PHY_7NM_QUIRK_V7_0,
+       .quirks = DSI_PHY_7NM_QUIRK_V7_2,
 };
 
 const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs = {
@@ -1525,5 +1525,5 @@ const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs = {
 #endif
        .io_start = { 0x9ac1000, 0x9ac4000 },
        .num_dsi_phy = 2,
-       .quirks = DSI_PHY_7NM_QUIRK_V7_0,
+       .quirks = DSI_PHY_7NM_QUIRK_V7_2,
 };