zynq_afx_nand arm armv7 zynq xilinx zynq zynq_afx:AFX_NAND
zynq_zc70x arm armv7 zynq xilinx zynq
zynq_zed arm armv7 zynq xilinx zynq
+zynq_cse_qspi arm armv7 zynq xilinx zynq zynq_cse:CSE_QSPI
omap5_uevm arm armv7 omap5_uevm ti omap5
dra7xx_evm arm armv7 dra7xx ti omap5
s5p_goni arm armv7 goni samsung s5pc1xx
#define CONFIG_SYS_SDRAM_BASE 0
#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
+/* TEXT BASE defines */
+#if defined(CONFIG_CSE_QSPI)
+# define CONFIG_SYS_TEXT_BASE 0xFFFC4800
+#else
+# define CONFIG_SYS_TEXT_BASE 0x04000000
+#endif
+
/* Total Size of Environment Sector */
#define CONFIG_ENV_SIZE (128 << 10)
/* Physical Memory map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0
-#define CONFIG_SYS_TEXT_BASE 0x04000000
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
--- /dev/null
+/*
+ * (C) Copyright 2013 Xilinx.
+ *
+ * Configuration settings for the Xilinx Zynq CSE board.
+ * See zynq_common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_CSE_H
+#define __CONFIG_ZYNQ_CSE_H
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ZYNQ_DCC
+#define _CONFIG_CMD_DEFAULT_H
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_ENV_IS_NOWHERE
+
+#if defined(CONFIG_CSE_QSPI)
+# define CONFIG_ZYNQ_QSPI
+#endif
+
+#include <configs/zynq_common.h>
+
+/* Undef unneeded configs */
+#undef CONFIG_SYS_SDRAM_BASE
+#undef CONFIG_OF_LIBFDT
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOARD_LATE_INIT
+#undef CONFIG_FPGA
+#undef CONFIG_FPGA_XILINX
+#undef CONFIG_FPGA_ZYNQPL
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_FIT
+#undef CONFIG_FIT_VERBOSE
+#undef CONFIG_CMD_GO
+#undef CONFIG_CMD_BOOTM
+#undef CONFIG_CMD_BOOTZ
+#undef CONFIG_BOOTCOMMAND
+#undef CONFIG_SYS_HUSH_PARSER
+#undef CONFIG_SYS_PROMPT_HUSH_PS2
+#undef CONFIG_BOOTDELAY
+#undef CONFIG_SYS_MALLOC_LEN
+#undef CONFIG_ENV_SIZE
+
+/* Define needed configs */
+#define CONFIG_CMD_MEMORY
+#define CONFIG_BOOTDELAY -1 /* -1 to Disable autoboot */
+#define CONFIG_SYS_MALLOC_LEN 0x4000
+
+#if defined(CONFIG_CSE_QSPI)
+# define PHYS_SDRAM_1_SIZE (256 * 1024)
+# define CONFIG_SYS_SDRAM_BASE 0xFFFD0000
+# define CONFIG_ENV_SIZE 1400
+#endif
+
+#endif /* __CONFIG_ZYNQ_CSE_H */