net: dsa: vsc73xx: fix port MAC configuration in full duplex mode

[ Upstream commit 63796bc2e97cd5ebcef60bad4953259d4ad11cb4 ]

According to the datasheet description ("Port Mode Procedure" in 5.6.2),
the VSC73XX_MAC_CFG_WEXC_DIS bit is configured only for half duplex mode.

The WEXC_DIS bit is responsible for MAC behavior after an excessive
collision. Let's set it as described in the datasheet.

Fixes: 05bd97fc559d ("net: dsa: Add Vitesse VSC73xx DSA router driver")
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vitesse-vsc73xx-core.c
index 4b031fefcec68279d8ed378c17b19ae572e44ce1..fc4030976bdce14fa770683356d70cb8da60dd28 100644 (file)
--- a/drivers/net/dsa/vitesse-vsc73xx-core.c
+++ b/drivers/net/dsa/vitesse-vsc73xx-core.c
@@ -817,6 +817,11 @@ static void vsc73xx_mac_link_up(struct phylink_config *config,
 
        if (duplex == DUPLEX_FULL)
                val |= VSC73XX_MAC_CFG_FDX;
+       else
+               /* In datasheet description ("Port Mode Procedure" in 5.6.2)
+                * this bit is configured only for half duplex.
+                */
+               val |= VSC73XX_MAC_CFG_WEXC_DIS;
 
        /* This routine is described in the datasheet (below ARBDISC register
         * description)
@@ -827,7 +832,6 @@ static void vsc73xx_mac_link_up(struct phylink_config *config,
        get_random_bytes(&seed, 1);
        val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET;
        val |= VSC73XX_MAC_CFG_SEED_LOAD;
-       val |= VSC73XX_MAC_CFG_WEXC_DIS;
        vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val);
 
        /* Flow control for the PHY facing ports: