drm/amdgpu: query block error count of ras module

Query block error count of ras module.

Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 81f72da5b2f084b0382f54d243938842cd295e3e..ff34e1c0d9e2c45432f75653be4f6d7eef4a8d86 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1543,9 +1543,36 @@ out_fini_err_data:
        return ret;
 }
 
+static int amdgpu_uniras_query_block_ecc(struct amdgpu_device *adev,
+                       struct ras_query_if *info)
+{
+       struct ras_cmd_block_ecc_info_req req = {0};
+       struct ras_cmd_block_ecc_info_rsp rsp = {0};
+       int ret;
+
+       if (!info)
+               return -EINVAL;
+
+       req.block_id = info->head.block;
+       req.subblock_id = info->head.sub_block_index;
+
+       ret = amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__GET_BLOCK_ECC_STATUS,
+                               &req, sizeof(req), &rsp, sizeof(rsp));
+       if (!ret) {
+               info->ce_count = rsp.ce_count;
+               info->ue_count = rsp.ue_count;
+               info->de_count = rsp.de_count;
+       }
+
+       return ret;
+}
+
 int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info)
 {
-       return amdgpu_ras_query_error_status_with_event(adev, info, RAS_EVENT_TYPE_INVALID);
+       if (amdgpu_uniras_enabled(adev))
+               return amdgpu_uniras_query_block_ecc(adev, info);
+       else
+               return amdgpu_ras_query_error_status_with_event(adev, info, RAS_EVENT_TYPE_INVALID);
 }
 
 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,