]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
ARM: dts: imx6ul[l]-tqma6ul[l]: add boot phase properties
authorMax Merchel <Max.Merchel@ew.tq-group.com>
Fri, 20 Feb 2026 14:31:03 +0000 (15:31 +0100)
committerFrank Li <Frank.Li@nxp.com>
Mon, 6 Apr 2026 01:35:30 +0000 (21:35 -0400)
dtschema/schemas/bootph.yaml describe various node usage during
boot phases with DT.

TQMa6UL need eMMC, I2C, GPIO and QSPI access during boot process.

Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi
arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi
arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi

index 2dd635a615cb8fb0972342cafd13e787b5441a5c..4fa98e6a66d7c135982c5c14043f7b2abdea1103 100644 (file)
@@ -26,6 +26,7 @@
        pinctrl-1 = <&pinctrl_i2c4_recovery>;
        scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
        sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       bootph-pre-ram;
        status = "okay";
 
        pfuze3000: pmic@8 {
        };
 };
 
+&gpio1 {
+       bootph-pre-ram;
+};
+
 &gpio4 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pmic>;
+       bootph-pre-ram;
 
        /*
         * PMIC & temperature sensor IRQ
 &qspi {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_qspi>;
+       bootph-pre-ram;
        status = "okay";
 
        flash0: flash@0 {
                spi-rx-bus-width = <4>;
                spi-tx-bus-width = <1>;
                vcc-supply = <&reg_vldo4>;
+               bootph-pre-ram;
 
                partitions {
                        compatible = "fixed-partitions";
        non-removable;
        no-sdio;
        no-sd;
+       bootph-all;
        status = "okay";
 };
 
                        /* PMIC irq */
                        MX6UL_PAD_CSI_DATA03__GPIO4_IO24        0x1b099
                >;
+               bootph-pre-ram;
        };
 };
index e2e95dd92263edb36ffb886f5f29a1fb05d56779..f81cd09fe0c7f15d18d67ae51f65bf08492c3f28 100644 (file)
@@ -33,6 +33,7 @@
                        /* rst */
                        MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
                >;
+               bootph-all;
        };
 
        pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
index 4b87e2dc70dcdf2289842b17c50883277a549378..11c8f1af417326828e9e072424424b6fb72305f4 100644 (file)
@@ -33,6 +33,7 @@
                        /* rst */
                        MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
                >;
+               bootph-all;
        };
 
        pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
index 5afb9046c202a73fde2ba5e0a915d4ba0a887fa1..5c90d0a3ee2e7286826165f56bdb94663c46c60b 100644 (file)
@@ -39,5 +39,6 @@
                        MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70b9
                        MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
                >;
+               bootph-pre-ram;
        };
 };
index ba84a4f70ebdee9d28cc5846e39ddac97b0e22f4..133961ee72831e810c77388d14d1b0705539b411 100644 (file)
@@ -44,5 +44,6 @@
                        MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a9
                        MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
                >;
+               bootph-pre-ram;
        };
 };
index 8541cb3f3b3e224213d79eb92d2b013f1cd8e382..1224ef132439717302bd45723218e856c848223b 100644 (file)
@@ -38,6 +38,7 @@
                        /* rst */
                        MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
                >;
+               bootph-all;
        };
 
        pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
index be593d47e3b1eca081a02a35709ee05a76d6d769..6dd1b359e0862c90d2f73dd333e4dd6eeca7d385 100644 (file)
@@ -38,6 +38,7 @@
                        /* rst */
                        MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
                >;
+               bootph-all;
        };
 
        pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {