arm64: dts: qcom: qcs615: Add CPU scaling clock node

Add cpufreq-hw node to support CPU frequency scaling.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250814-qcs615-mm-cpu-dt-v6-v6-2-a06f69928ab5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi
index d72647f0045b85b6960b814d3ce74869f681a320..47ace8d414c0c4b928eef83f2c3a93d1850b5a30 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi
@@ -36,6 +36,8 @@
                        capacity-dmips-mhz = <1024>;
                        dynamic-power-coefficient = <100>;
                        next-level-cache = <&l2_0>;
+                       clocks = <&cpufreq_hw 0>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
 
                        l2_0: l2-cache {
@@ -56,6 +58,8 @@
                        capacity-dmips-mhz = <1024>;
                        dynamic-power-coefficient = <100>;
                        next-level-cache = <&l2_100>;
+                       clocks = <&cpufreq_hw 0>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
 
                        l2_100: l2-cache {
                              compatible = "cache";
@@ -75,6 +79,8 @@
                        capacity-dmips-mhz = <1024>;
                        dynamic-power-coefficient = <100>;
                        next-level-cache = <&l2_200>;
+                       clocks = <&cpufreq_hw 0>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
 
                        l2_200: l2-cache {
                              compatible = "cache";
@@ -94,6 +100,8 @@
                        capacity-dmips-mhz = <1024>;
                        dynamic-power-coefficient = <100>;
                        next-level-cache = <&l2_300>;
+                       clocks = <&cpufreq_hw 0>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
 
                        l2_300: l2-cache {
                              compatible = "cache";
@@ -113,6 +121,8 @@
                        capacity-dmips-mhz = <1024>;
                        dynamic-power-coefficient = <100>;
                        next-level-cache = <&l2_400>;
+                       clocks = <&cpufreq_hw 0>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
 
                        l2_400: l2-cache {
                              compatible = "cache";
@@ -132,6 +142,8 @@
                        capacity-dmips-mhz = <1024>;
                        dynamic-power-coefficient = <100>;
                        next-level-cache = <&l2_500>;
+                       clocks = <&cpufreq_hw 0>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
 
                        l2_500: l2-cache {
                              compatible = "cache";
@@ -151,6 +163,8 @@
                        capacity-dmips-mhz = <1740>;
                        dynamic-power-coefficient = <404>;
                        next-level-cache = <&l2_600>;
+                       clocks = <&cpufreq_hw 1>;
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        #cooling-cells = <2>;
 
                        l2_600: l2-cache {
@@ -171,6 +185,8 @@
                        capacity-dmips-mhz = <1740>;
                        dynamic-power-coefficient = <404>;
                        next-level-cache = <&l2_700>;
+                       clocks = <&cpufreq_hw 1>;
+                       qcom,freq-domain = <&cpufreq_hw 1>;
 
                        l2_700: l2-cache {
                              compatible = "cache";
@@ -4142,6 +4158,19 @@
                                };
                        };
                };
+
+               cpufreq_hw: cpufreq@18323000 {
+                       compatible = "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw";
+                       reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
+                       reg-names = "freq-domain0", "freq-domain1";
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+                       clock-names = "xo", "alternate";
+
+                       #freq-domain-cells = <1>;
+                       #clock-cells = <1>;
+               };
+
        };
 
        arch_timer: timer {